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SY100E154JZ Datasheet(PDF) 1 Page - Micrel Semiconductor |
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SY100E154JZ Datasheet(HTML) 1 Page - Micrel Semiconductor |
1 / 4 page 1 SY10E154 SY100E154 Micrel, Inc. M9999-032006 hbwhelp@micrel.com or (408) 955-1690 s 750ps max. LEN to output s Extended 100E VEE range of –4.2V to –5.5V s 700ps max. D to output s Differential outputs s Asynchronous Master Reset s Dual latch-enables s Fully compatible with industry standard 10KH, 100K ECL levels s Internal 75K Ω input pulldown resistors s Fully compatible with Motorola MC10E/100E154 s Available in 28-pin PLCC package FEATURES 5-BIT 2:1 MUX-LATCH The SY10/100E154 offer five 2:1 multiplexers followed by latches with differential outputs, designed for use in new, high-performance ECL systems. The two external Latch-Enable signals (LEN1, LEN2) are gated through a logical OR operation before use as control for the five latches. When both LEN1 and LEN2 are at a logic LOW, the latches are transparent, thus presenting the data from the multiplexers at the output pins. If either LEN1 or LEN2 (or both) are at a logic HIGH, the outputs are latched. The multiplexer operation is controlled by the SEL(Select) signal which selects one of the two bits of input data at each mux to be passed through. The MR (Master Reset) signal operates asynchronously to make all Q outputs go to a logic LOW. DESCRIPTION Rev.: E Amendment: /0 Issue Date: March 2006 SY10E154 SY100E154 BLOCK DIAGRAM Pin Function D0a–D4a Input Data a D0b–D4b Input Data b SEL Data Select Input LEN1, LEN2 Latch Enables MR Master Reset Q0–Q4 True Outputs Q0–Q4 Inverted Outputs VCCO VCC to Output PIN NAMES MR D R D0a LEN1 LEN2 Q E N Q MUX SEL SEL D0b D R D1a Q E N Q MUX D1b D R D2a Q E N Q MUX D2b D R D3a Q E N Q MUX D3b D R D4a Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 Q4 Q4 Q E N Q MUX D4b SEL SEL SEL SEL |
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