6

SY10E136

SY100E136

Micrel, Inc.

M9999-032006

hbwhelp@micrel.com or (408) 955-1690

LOGIC DIAGRAM

APPLICATIONS INFORMATION

Overview

The SY10E/100E136 are 6-bit synchronous, presettable,

pins, the user can select between preset, count up, count

down and hold count. The Master Reset pin will reset the

flops.

Unlike previous 136-type counters, the carry-out

outputs will go to a high state during the preset operation.

In addition, since the carry-out outputs are registered, they

will not go low if terminal count is loaded into the register.

The look-ahead-carry-out output functions similarly.

Note from the schematic the use of the master information

from the least significant bits for control of the two carry-out

functions. This architecture not only reduces the carry-out

delay, but is essential to incorporate the registered carry-

out functions. In addition to being faster, the resulting carry-

out signals are stable and glitch free because these functions

are registered.

Cascading Multiple E136 Devices

Many applications require counters significantly larger than

the 6 bits available with the E136. For these applications,

several E136 devices can be cascaded to increase the bit

width of the counter to meet the needs of the application.

In the past, cascading several 136-type universal counters

necessarily impacted the maximum count frequency of the

resulting counter chain. This performance impact was the

result of the terminal count signal of the lower order counters

Figure 1. 24-bit Cascaded E136 Counter

having to ripple through the entire counter chain.

As a

result, past counters of this type were not widely used in

large bit counter applications.

An alternative counter architecture similar to the E016

binary counter was implemented to alleviate the need to

ripple propagate the terminal count signal. Unfortunately,

these types of counters require external gating for cascading

designs of more than two devices. In addition to requiring

additional components, these external gates limit the

cascaded count frequency to a value less than the free

running count frequency of a single counter. Although there

is a performance impact with this type of architecture, it is

minor compared to the impact of the ripple propagate

designs. As a result, the E016-type counters have been

used extensively in applications requiring very high speed,

wide bit width synchronous counters.

Several improvements have been incorporated to past

universal counter designs in the E136 universal counter.

These enhancements make the E136 the unparalleled leader

in its class. With the addition of look-ahead-carry features

on the terminal count signal, very large counter chains can

be designed which function at very nearly the same clock

frequency as a single free running device. More importantly,

these counter chains require no external gating. Figure 1

below illustrates the interconnect scheme for using the look-

ahead-carry features of the E136 counter.

CLK

CLOCK

"LO"

"LO"

LSB

"LO"

MSB

CLK

111101

111110

111111

CLK

CLK

CLK

000001

000000