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NLSF595MNR2 Datasheet(PDF) 4 Page - ON Semiconductor |
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NLSF595MNR2 Datasheet(HTML) 4 Page - ON Semiconductor |
4 / 14 page NLSF595 http://onsemi.com 4 MAXIMUM RATINGS Symbol Parameter Value Unit VCC Positive DC Supply Voltage −0.5 to +7.0 V VIN Digital Input Voltage −0.5 to +7.0 V VOUT DC Output Voltage −0.5 to VCC +7.0 V IIK Input Diode Current −20 mA IOK Output Diode Current $50 mA IOUT DC Output Current, per Pin +50 mA ICC DC Supply Current, VCC and GND Pins $75 mA PD Power Dissipation in Still Air 450 mW TSTG Storage Temperature Range −65 to +150 °C ILATCHUP Latchup Performance Above VCC and Below GND at 125°C (Note 1) $300 mA qJA Thermal Resistance, Junction−to−Ambient 128 °C/W Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. Tested to EIA/JESD78 RECOMMENDED OPERATING CONDITIONS Symbol Characteristics Min Max Unit VCC DC Supply Voltage 2.0 5.5 V VIN DC Input Voltage 0 5.5 V VOUT DC Output Voltage 0 VCC V TA Operating Temperature Range, all Package Types −55 125 °C tr, tf Input Rise or Fall Time VCC = 3.3 V + 0.3 V VCC = 5.0 V + 0.5 V 0 50 15 ns/V FUNCTION TABLE Operation Inputs Resulting Function Reset (SCLR) Serial Input (SI) Shift Clock (SCK) Reg Clock (RCK) Output Enable (OE) Shift Register Contents Storage Register Contents Serial Output (SQH) Parallel Outputs (QA − QH) Clear shift register L X X L, H, ↓ L L U L U Shift data into shift register H D ↑ L, H, ↓ L D →SRA; SRN→SRN+1 U SRG→SRH U Registers remains unchanged H X L, H, ↓ X L U ** U ** Transfer shift register contents to storage register H X L, H, ↓ ↑ L U SRN³STRN * SRN Storage register remains unchanged X X X L, H, ↓ L * U * U Enable parallel outputs X X X X L * ** * Enabled Force outputs into high impedance state X X X X H * ** * Z SR = shift register contents D = data (L, H) logic level ↓ = High−to−Low * = depends on Reset and Shift Clock inputs STR = storage register contents U = remains unchanged ↑ = Low−to−High ** = depends on Register Clock input |
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