TNL17SZ74USG datasheet(1/6 Pages) ONSEMI

Part #	TNL17SZ74USG

Description	Single D Flip Flop

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Manufacturer	ONSEMI [ON Semiconductor]

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April, 2006 − Rev. 4

1

Publication Order Number:

NL17SZ74/D

NL17SZ74

Single D Flip Flop

The NL17SZ74 is a high performance, full function Edge triggered

D Flip Flop, with all the features of a standard logic device such as the

74LCX74.

Features

• Extremely High Speed: tPD 2.6 ns (typical) at VCC = 5.0 V

• Designed for 1.65 V to 5.5 V VCC Operation

• 5.0 V Tolerant Inputs − Interface Capability with 5.0 V TTL Logic

• LVTTL Compatible

• LVCMOS Compatible

• 24 mA Balanced Output Sink and Source Capability

• Near Zero Static Supply Current (10 mA) Substantially Reduces

System Power Requirements

• Replacement for NC7SZ74

• Tiny Ultra Small Package Only 2.1 X 3.0 mm

• High ESD Ratings: 2000 V Human Body Model

High ESD Ratings:

200 V Machine Model

• Chip Complexity: FET = 64

• Pb−Free Packages are Available

TRUTH TABLE

Inputs

Outputs

Operating Mode

PR

CLR

CP

D

Q

L

H

L

H

L

X

H

L

H

L

H

Asynchronous Set

Asynchronous Clear

Undetermined

H

↑

h

l

H

L

H

Load and Read Register

H

↑

X

NC

Hold

H

= High Voltage Level

h

= High Voltage Level One Setup Time Prior to the Low−to−High

Clock Transition

L

= Low Voltage Level

l

= Low Voltage Level One Setup Time Prior to the Low−to−High

Clock Transition

NC

= No Change

X

= High or Low Voltage Level and Transitions are Acceptable

↑

= Low−to−High Transition

↑

= Not a Low−to−High Transition

For ICC reasons, DO NOT FLOAT Inputs

http://onsemi.com

See detailed ordering and shipping information in the package

dimensions section on page 2 of this data sheet.

ORDERING INFORMATION

MARKING

DIAGRAM

US8

US SUFFIX

CASE 493

PINOUT DIAGRAM

VCC

PR

CLR

Q

CP

D

Q

GND

1

2

3

4

8

7

6

5

Q

PR

7

5

D

2

CP

1

CLR

6

Q

3

VCC = 8, GND = 4

LOGIC DIAGRAM

M

= Date Code

G

= Pb−Free Package

MH M

G

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