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NE570DR2 Datasheet(PDF) 7 Page - ON Semiconductor |
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NE570DR2 Datasheet(HTML) 7 Page - ON Semiconductor |
7 / 10 page NE570 http://onsemi.com 7 At very high frequencies, the response of the rectifier will fall off. The roll−off will be more pronounced at lower input levels due to the increasing amount of gain required to switch between Q5 or Q6 conducting. The rectifier frequency response for input levels of 0 dBm, −20 dBm, and −40 dBm is shown in Figure 11. The response at all three levels is flat to well above the audio range. 0 3 10 k 1 MEG INPUT = 0 dBm −20 dBm −40 dBm FREQUENCY (Hz) Figure 11. Rectifier Frequency Response vs. Input Level VARIABLE GAIN CELL Figure 12 is a diagram of the variable gain cell. This is a linearized two−quadrant transconductance multiplier. Q1, Q2 and the op amp provide a predistorted drive signal for the gain control pair, Q3 and Q4. The gain is controlled by IG and a current mirror provides the output current. V+ V− Q2 Q1 NOTE: IOUT = IG I1 R2 20 k W VIN IIN I2 ( = 2 I1 ) 280 mA − + I1 140 mA Q4 Q3 IG IIN = VIN R2 IG I1 Figure 12. Simplified DG Cell Schematic The op amp maintains the base and collector of Q1 at ground potential (VREF) by controlling the base of Q2. The input current IIN (= VIN/R2) is thus forced to flow through Q1 along with the current I1, so IC1 = I1 + IIN. Since I2 has been set at twice the value of I1, the current through Q2 is: I2 * (I1 ) IIN) + I1 * IIN + IC2. The op amp has thus forced a linear current swing between Q1 and Q2 by providing the proper drive to the base of Q2. This drive signal will be linear for small signals, but very non−linear for large signals, since it is compensating for the non−linearity of the differential pair, Q1 and Q2, under large signal conditions. The key to the circuit is that this same predistorted drive signal is applied to the gain control pair, Q3 and Q4. When two differential pairs of transistors have the same signal applied, their collector current ratios will be identical regardless of the magnitude of the currents. This gives us: I C1 I C2 + I C4 I C3 + I 1 ) IIN I 1 * IIN plus the relationships IG = IC3 + IC4 and IOUT = IC4 − IC3 will yield the multiplier transfer function, I OUT + I G I 1 I IN + V IN R 2 I G I 1 This equation is linear and temperature−insensitive, but it assumes ideal transistors. 4 3 2 1 0.34 −6 0 +6 4 mV 3 mV 2 mv 1 mV INPUT LEVEL (dBm) VOS = 5 mV Figure 13. DG Cell Distortion vs. Offset Voltage If the transistors are not perfectly matched, a parabolic, non−linearity is generated, which results in second harmonic distortion. Figure 13 gives an indication of the magnitude of the distortion caused by a given input level and offset voltage. The distortion is linearly proportional to the magnitude of the offset and the input level. Saturation of the gain cell occurs at a +8.0 dBm level. At a nominal operating level of 0 dBm, a 1.0 mV offset will yield 0.34% of second harmonic distortion. Most circuits are somewhat better than |
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