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NE5517 Datasheet(PDF) 1 Page - ON Semiconductor |
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NE5517 Datasheet(HTML) 1 Page - ON Semiconductor |
1 / 14 page © Semiconductor Components Industries, LLC, 2006 April, 2006 − Rev. 3 1 Publication Order Number: NE5517/D NE5517, NE5517A, AU5517 Dual Operational Transconductance Amplifier The AU5517 and NE5517 contain two current-controlled transconductance amplifiers, each with a differential input and push-pull output. The AU5517/NE5517 offers significant design and performance advantages over similar devices for all types of programmable gain applications. Circuit performance is enhanced through the use of linearizing diodes at the inputs which enable a 10 dB signal-to-noise improvement referenced to 0.5% THD. The AU5517/NE5517 is suited for a wide variety of industrial and consumer applications. Constant impedance of the buffers on the chip allow general use of the AU5517/NE5517. These buffers are made of Darlington transistors and a biasing network that virtually eliminate the change of offset voltage due to a burst in the bias current IABC, hence eliminating the audible noise that could otherwise be heard in high quality audio applications. Features • Constant Impedance Buffers • DVBE of Buffer is Constant with Amplifier IBIAS Change • Excellent Matching Between Amplifiers • Linearizing Diodes • High Output Signal-to-Noise Ratio • Pb−Free Packages are Available* Applications • Multiplexers • Timers • Electronic Music Synthesizers • Dolby® HX Systems • Current-Controlled Amplifiers, Filters • Current-Controlled Oscillators, Impedances *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com PIN CONNECTIONS See detailed ordering and shipping information in the package dimensions section on page 13 of this data sheet. ORDERING INFORMATION 1 2 3 4 5 6 7 8 9 10 11 12 13 14 16 15 IABCa Da +INa −INa VOa V− INBUFFERa VOBUFFERa IABCb Db +INb −INb VOb V+ INBUFFERb VOBUFFERb N, D Packages (Top View) PDIP−16 N SUFFIX CASE 648 1 SOIC−16 D SUFFIX CASE 751B 1 MARKING DIAGRAMS NE5517yy AWLYYWWG xx = AU or NE yy = AN or N A = Assembly Location WL = Wafer Lot YY, Y = Year WW = Work Week G = Pb−Free Package xx5517DG AWLYWW 1 1 |
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