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ATTINY26L Datasheet(PDF) 8 Page - ATMEL Corporation |
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ATTINY26L Datasheet(HTML) 8 Page - ATMEL Corporation |
8 / 185 page 8 ATtiny26(L) 1477I–AVR–10/06 AVR CPU Core Architectural Overview The fast-access Register File concept contains 32 x 8-bit general purpose working reg- isters with a single clock cycle access time. This means that during one single clock cycle, one ALU (Arithmetic Logic Unit) operation is executed. Two operands are output from the Register File, the operation is executed, and the result is stored back in the Register File – in one clock cycle. Six of the 32 registers can be used as 16-bit pointers for indirect memory access. These pointers are called the X-, Y-, and Z-pointers, and they can address the Register File and the Flash program memory. Figure 2. The ATtiny26(L) AVR Enhanced RISC Architecture The ALU supports arithmetic and logic functions between registers or between a con- stant and a register. Single register operations are also executed in the ALU. Figure 2 shows the ATtiny26(L) AVR Enhanced RISC microcontroller architecture. In addition to the register operation, the conventional memory addressing modes can be used on the Register File as well. This is enabled by the fact that the Register File is assigned the 32 lowermost Data Space addresses ($00 - $1F), allowing them to be accessed as though they were ordinary memory locations. The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, Timer/Counters, A/D Converters, and other I/O functions. The I/O Memory can be accessed directly, or as the Data Space locations following those of the Register File, $20 - $5F. 1024 x 16 Program FLASH Instruction Register Instruction Decoder Program Counter Control Lines 32 x 8 General Purpose Registers ALU Status and Test Control Registers Interrupt Unit 2 x 8-bit Timer/Counter Universal Serial Interface Watchdog Timer Analog Comparator I/O Lines 8-bit Data Bus ISP Unit ADC 128 x 8 SRAM 128 byte EEPROM |
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