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NCV4269D1G Datasheet(PDF) 2 Page - ON Semiconductor |
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NCV4269D1G Datasheet(HTML) 2 Page - ON Semiconductor |
2 / 16 page NCV4269 http://onsemi.com 2 I RO Q SO RADJ D Figure 1. Block Diagram GND SI Reference or RRO RSO Error Amplifier Reference and Trim Current and Saturation Control + − PIN CONNECTIONS SO RO Q GND GND GND GND GND 114 GND GND I D SI RADJ 1 20 NC NC GND GND GND GND GND GND GND GND NC NC I D SI RADJ Q NC SO RO SO−20L SO−14 GND D 18 RO RADJ SO SI Q I SO−8 PACKAGE PIN DESCRIPTION Package Pin Number Pin Symbol Function SO−8 SO−14 SO−20L 3 1 1 RADJ Reset Threshold Adjust; if not used to connect to GND. 4 2 2 D Reset Delay; To Set Time Delay, Connect to GND with Capacitor 5 3, 4, 5, 6, 10, 11, 12 4, 5, 6, 7, 14, 15, 16, 17 GND Ground − − 3, 8, 9, 13, 18 NC No connection to these pins from the IC. 6 7 10 RO Reset Output; The Open−Collector Output has a 20 k W Pullup Resistor to Q. Leave Open if Not Used. 7 8 11 SO Sense Output; This Open−Collector Output is Internally Pulled Up by 20 k W pullup resistor to Q. If not used, keep open. 8 9 12 Q 5 V Output; Connect to GND with a 10 mF Capacitor, ESR < 10 W. 1 13 19 I Input; Connect to GND Directly at the IC with a Ceramic Capacitor. 2 14 20 SI Sense Input; If not used, Connect to Q. |
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