ATMEGA161-4PI datasheet(8/159 Pages) ATMEL

Part #	ATMEGA161-4PI

Description	8-bit Microcontroller with 16K Bytes of In-System Programmable Flash

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Manufacturer	ATMEL [ATMEL Corporation]

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ATmega161(L)

1228D–AVR–02/07

In addition to the register operation, the conventional Memory Addressing modes can be

used on the Register File. This is enabled by the fact that the Register File is assigned

the 32 lowermost Data Space addresses ($00 - $1F), allowing them to be accessed as

though they were ordinary memory locations.

The I/O memory space contains 64 addresses for CPU peripheral functions such as

Control Registers, Timer/Counters, and other I/O functions. The I/O memory can be

accessed directly or as the Data Space locations following those of the Register File,

$20 - $5F.

The AVR uses a Harvard architecture concept – with separate memories and buses for

program and data. The Program memory is executed with a two-stage pipeline. While

one instruction is being executed, the next instruction is pre-fetched from the Program

memory. This concept enables instructions to be executed in every clock cycle. The

Program memory is Self-programmable Flash memory.

With the jump and call instructions, the whole 8K word address space is directly

accessed. Most AVR instructions have a single 16-bit word format. Every Program

memory address contains a 16- or 32-bit instruction.

During interrupts and subroutine calls, the return address Program Counter (PC) is

stored on the Stack. The Stack is effectively allocated in the general data SRAM and,

consequently, the Stack size is only limited by the total SRAM size and the usage of the

SRAM. All user programs must initialize the SP (Stack Pointer) in the reset routine

(before subroutines or interrupts are executed). The 16-bit Stack Pointer is read/write

accessible in the I/O space.

The 1K byte data SRAM can be easily accessed through the five different Addressing

modes supported in the AVR architecture.

The memory spaces in the AVR architecture are all linear and regular memory maps.

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