ATMEGA103L-4AC datasheet(8/141 Pages) ATMEL

Part #	ATMEGA103L-4AC

Description	8-bit Microcontroller with 128K Bytes In-System Programmable Flash

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Manufacturer	ATMEL [ATMEL Corporation]

Direct Link	http://www.atmel.com

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ATmega103(L)

0945I–AVR–02/07

Architectural

Overview

Figure 4. The ATmega103(L) AVR RISC Architecture

The AVR uses a Harvard architecture concept – with separate memories and buses for

program and data. The Program memory is accessed with a single-level pipeline. While

one instruction is being executed, the next instruction is pre-fetched from the Program

memory. This concept enables instructions to be executed in every clock cycle. The

Program memory is In-System Programmable Flash memory. With a few exceptions,

AVR instructions have a single 16-bit word format, meaning that every Program memory

address contains a single 16-bit instruction.

During interrupts and subroutine calls, the return address Program Counter (PC) is

stored on the Stack. The Stack is effectively allocated in the general data SRAM and,

consequently, the Stack size is only limited by the total SRAM size and the usage of the

SRAM. All user programs must initialize the SP in the reset routine (before subroutines

or interrupts are executed). The 16-bit Stack Pointer (SP) is read/write accessible in the

I/O space.

The 4000 bytes data SRAM can be easily accessed through the five different address-

ing modes supported in the AVR architecture.

A flexible interrupt module has its control registers in the I/O space with an additional

Global Interrupt Enable bit in the Status Register. All the different interrupts have a sep-

64K x 16

Program

Memory

Instruction

Register

Instruction

Decoder

Program

Counter

Control Lines

32 x 8

General

Purpose

Registers

ALU

Status

and Test

4K x 8

EEPROM

Peripherals

Data Bus 8-bit

AVR ATmega103(L) Architecture

4K x 8

Data

SRAM

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ATMEGA103L-4AC Datasheet(PDF) 8 Page - ATMEL Corporation

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