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AT89C51-24PI Datasheet(PDF) 5 Page - ATMEL Corporation |
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AT89C51-24PI Datasheet(HTML) 5 Page - ATMEL Corporation |
5 / 17 page AT89C51 5 Figure 2. External Clock Drive Configuration Power-down Mode In the power-down mode, the oscillator is stopped, and the instruction that invokes power-down is the last instruction executed. The on-chip RAM and Special Function Regis- ters retain their values until the power-down mode is terminated. The only exit from power-down is a hardware reset. Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be activated before V CC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize. Program Memory Lock Bits On the chip are three lock bits which can be left unpro- grammed (U) or can be programmed (P) to obtain the additional features listed in the table below. When lock bit 1 is programmed, the logic level at the EA pin is sampled and latched during reset. If the device is pow- ered up without a reset, the latch initializes to a random value, and holds that value until reset is activated. It is nec- essary that the latched value of EA be in agreement with the current logic level at that pin in order for the device to function properly. Lock Bit Protection Modes Program Lock Bits Protection Type LB1 LB2 LB3 1 U U U No program lock features 2 P U U MOVC instructions executed from external program memory are disabled from fetching code bytes from internal memory, EA is sampled and latched on reset, and further programming of the Flash is disabled 3 P P U Same as mode 2, also verify is disabled 4 P P P Same as mode 3, also external execution is disabled |
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