6

AT93C46/56/66

0172Z–SEEPR–9/05

Functional

Description

The AT93C46/56/66 is accessed via a simple and versatile three-wire serial communi-

cation interface. Device operation is controlled by seven instructions issued by the host

processor. A valid instruction starts with a rising edge of CS and consists of a start bit

(logic “1”) followed by the appropriate op code and the desired memory address

location.

READ (READ): The Read (READ) instruction contains the address code for the mem-

ory location to be read. After the instruction and address are decoded, data from the

selected memory location is available at the serial output pin DO. Output data changes

are synchronized with the rising edges of serial clock SK. It should be noted that a

dummy bit (logic “0”) precedes the 8- or 16-bit data output string.

ERASE/WRITE ENABLE (EWEN): To assure data integrity, the part automatically goes

into the Erase/Write Disable (EWDS) state when power is first applied. An Erase/Write

Enable (EWEN) instruction must be executed first before any programming instructions

can be carried out. Please note that once in the EWEN state, programming remains

enabled until an EWDS instruction is executed or V

ERASE (ERASE): The Erase (ERASE) instruction programs all bits in the specified

memory location to the logical “1” state. The self-timed erase cycle starts once the

Erase instruction and address are decoded. The DO pin outputs the Ready/Busy status

of the part if CS is brought high after being kept low for a minimum of 250 ns (t

logic “1” at pin DO indicates that the selected memory location has been erased and the

part is ready for another instruction.

WRITE (WRITE): The Write (WRITE) instruction contains the 8 or 16 bits of data to be

written into the specified memory location. The self-timed programming cycle t

after the last bit of data is received at serial data input pin DI. The DO pin outputs the

Read/Busy status of the part if CS is brought high after being kept low for a minimum of

250 ns (t

indicates that the memory location at the specified address has been written with the

data pattern contained in the instruction and the part is ready for further instructions. A

Ready/Busy status cannot be obtained if the CS is brought high after the end of the self-

timed programming cycle tWP.

ERASE ALL (ERAL): The Erase All (ERAL) instruction programs every bit in the mem-

ory array to the logic “1” state and is primarily used for testing purposes. The DO pin

outputs the Ready/Busy status of the part if CS is brought high after being kept low for a

minimum of 250 ns (t

WRITE ALL (WRAL): The Write All (WRAL) instruction programs all memory locations

with the data patterns specified in the instruction. The DO pin outputs the Ready/Busy

status of the part if CS is brought high after being kept low for a minimum of 250 ns (t

The WRAL instruction is valid only at V

ERASE/WRITE DISABLE (EWDS): To protect against accidental data disturb, the

Erase/Write Disable (EWDS) instruction disables all programming modes and should be

executed after all programming operations. The operation of the Read instruction is

independent of both the EWEN and EWDS instructions and can be executed at any

time.