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SSM2160S-REEL Datasheet(PDF) 5 Page - Analog Devices |
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SSM2160S-REEL Datasheet(HTML) 5 Page - Analog Devices |
5 / 16 page REV. A SSM2160 –5– PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Function 1V+Positive Power Supply. Refer to the Application Information section for details on the power supply. 2 AGND Internal Ground Reference for the Audio Circuitry. When operating the SSM2160 from dual supplies, AGND should be connected to ground. When operating from a single supply, AGND should be connected to VREF, the internally generated voltage reference. AGND may also be connected to an external reference. Refer to the Application Information section for more information on the power supply. 3VREF VREF is the internally generated ground reference for the audio circuitry obtained from a buffered divider between V+ and V–. In a dual-supply application with the AGND pin connected to ground, VREF should be left floating. In a single-supply application, VREF should be connected to AGND. Refer to the Application Information section for more information on the power supply. 4 CH1 OUT Audio Output from Channel 1 5 CH1 IN Audio Input to Channel 1 6 CH3 OUT Audio Output from Channel 3 7 CH3 IN Audio Input to Channel 3 8 CH5 OUT Audio Output from Channel 5 9 CH5 IN Audio Input to Channel 5 10 WRITE A logic low voltage enables the SSM2160 to receive information at the DATA input (Pin 15). A logic high retains data at their previous settings (Figure 1). Serves as CHIP SELECT. 11 LD Loads the Information Retained by WRITE into the SSM2160 at logic low (Figure 1). 12 V– Negative Power Supply. Connect to ground in a single-supply application. Refer to the Application Information section for details on the power supply. 13 DGND Digital Ground Reference. This pin should always be connected to ground. All digital inputs, including WRITE, LD, CLK, and DATA are TTL input compatible; drive currents are returned to DGND. 14 CLK Clock Input. It is positive edge triggered (Figure 1). 15 DATA Channel and master control information flows MSB first into the DATA pin. Refer to the Address/Data Decoding Truth Table, Figure 7, for information on how to control the VCAs. 16 CH6 IN Audio Input to Channel 6 17 CH6 OUT Audio Output from Channel 6 18 CH4 IN Audio Input to Channel 4 19 CH4 OUT Audio Output from Channel 4 20 CH2 IN Audio Input to Channel 2 21 CH2 OUT Audio Output from Channel 2 22 MSTR SET Connected to the inverting input of an I-V converting op amp. It is used to generate a master control voltage from the master control DAC current output. A resistor connected from MSTR OUT to MSTR SET reduces the step size of the master control. See the Master/Channel Step Sizes section for more details. A 10 µF capacitor should be connected from MSTR OUT to MSTR SET to eliminate the zipper noise in the master control. 23 MSTR OUT Connected to the output of the I-V converting op amp. See MSTR SET description. 24 CH SET The step size of the channel control can be increased by connecting a resistor from CH SET to V+. No connection to CH SET is required if the default value of 1 dB per step is desired. Minimum of 10 Ω external resistor. See the Master/Channel Step Sizes section for details. |
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