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MCIMX31 Datasheet(PDF) 8 Page - Freescale Semiconductor, Inc |
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MCIMX31 Datasheet(HTML) 8 Page - Freescale Semiconductor, Inc |
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8 / 108 page  i.MX31/i.MX31L Advance Information, Rev. 2.3 8 Freescale Semiconductor Functional Description and Application Information SCC Security Controller Module Security The SCC is a hardware component composed of two blocks—the Secure RAM module, and the Security Monitor. The Secure RAM provides a way of securely storing sensitive information. – SDHC Secured Digital Host Controller Connectivity Peripheral The SDHC controls the MMC (MultiMediaCard), SD (Secure Digital) memory, and I/O cards by sending commands to cards and performing data accesses to and from the cards. 4.3.19/82 SDMA Smart Direct Memory Access System Control Peripheral The SDMA controller maximizes the system’s performance by relieving the ARM core of the task of bulk data transfer from memory to memory or between memory and on-chip peripherals. – SIM Subscriber Identification Module Connectivity Peripheral The SIM interfaces to an external Subscriber Identification Card. It is an asynchronous serial interface adapted for Smart Card communication for e-commerce applications. 4.3.20/83 SJC Secure JTAG Controller Debug The SJC provides debug and test control with maximum security and provides a flexible architecture for future derivatives or future multi-cores architecture. 4.3.21/87 SSI Synchronous Serial Interface Multimedia Peripheral The SSI is a full-duplex, serial port that allows the device to communicate with a variety of serial devices, such as standard codecs, Digital Signal Processors (DSPs), microprocessors, peripherals, and popular industry audio codecs that implement the inter-IC sound bus standard (I2S) and Intel AC97 standard. 4.3.22/89 UART Universal Asynchronous Receiver/Trans mitter Connectivity Peripheral The UART provides serial communication capability with external devices through an RS-232 cable or through use of external circuitry that converts infrared signals to electrical signals (for reception) or transforms electrical signals to signals that drive an infrared LED (for transmission) to provide low speed IrDA compatibility. – USB Universal Serial Bus— 2 Host Controllers and 1 OTG (On-The-Go) Connectivity Peripherals • USB Host 1 is designed to support transceiverless connection to the on-board peripherals in Low Speed and Full Speed mode, and connection to the ULPI (UTMI+ Low-Pin Count) and Legacy Full Speed transceivers. • USB Host 2 is designed to support transceiverless connection to the Cellular Modem Baseband Processor. • The USB-OTG controller offers HS/FS/LS capabilities in Host mode and HS/FS in device mode. In Host mode, the controller supports direct connection of a FS/LS device (without external hub). In device (bypass) mode, the OTG port functions as gateway between the Host 1 Port and the OTG transceiver. 4.3.23/97 WDOG Watchdog Timer Module Timer Peripheral The WDOG module protects against system failures by providing a method for the system to recover from unexpected events or programming errors. – Table 3. Digital and Analog Modules (continued) Block Mnemonic Block Name Functional Grouping Brief Description Section/ Page |
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