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AT45D021A-JC Datasheet(PDF) 7 Page - ATMEL Corporation |
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AT45D021A-JC Datasheet(HTML) 7 Page - ATMEL Corporation |
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7 / 28 page  AT45D021A 7 of main memory. The operation is internally self-timed and should take place in a maximum time of t EP. During this time, the status register will indicate that the part is busy. If a sector is programmed or reprogrammed sequentially page-by-page, then the programming algorithm shown in Figure 1 on page 24 is recommended. Otherwise, if multi- ple bytes in a page or several pages are programmed randomly in a sector, then the programming algorithm shown in Figure 2 on page 25 is recommended. Operation Mode Summary The modes described can be separated into two groups – modes which make use of the Flash memory array (Group A) and modes which do not make use of the Flash memory array (Group B). Group A modes consist of: 1. Main Memory Page Read 2. Main Memory Page to Buffer 1 (or 2) Transfer 3. Main Memory Page to Buffer 1 (or 2) Compare 4. Buffer 1 (or 2) to Main Memory Page Program with Built-in Erase 5. Buffer 1 (or 2) to Main Memory Page Program without Built-in Erase 6. Page Erase 7. Block Erase 8. Main Memory Page Program through Buffer 9. Auto Page Rewrite Group B modes consist of: 1. Buffer 1 (or 2) Read 2. Buffer 1 (or 2) Write 3. Status Register Read If a Group A mode is in progress (not fully completed) then another mode in Group A should not be started. However, during this time in which a Group A mode is in progress, modes in Group B can be started. This gives the Serial DataFlash the ability to virtually accommodate a continuous data stream. While data is being programmed into main memory from buffer 1, data can be loaded into buffer 2 (or vice versa). See application note AN-4 (“Using Atmel’s Serial DataFlash”) for more details. Pin Descriptions SERIAL INPUT (SI): The SI pin is an input only pin and is used to shift data into the device. The SI pin is used for all data input including opcodes and address sequences. SERIAL OUTPUT (SO): The SO pin is an output only pin and is used to shift data out from the device. SERIAL CLOCK (SCK): The SCK pin is an input only pin and is used to control the flow of data to and from the DataFlash. Data is always clocked into the device on the rising edge of SCK and clocked out of the device on the falling edge of SCK. CHIP SELECT (CS): The DataFlash is selected when the CS pin is low. When the device is not selected, data will not be accepted on the SI pin, and the SO pin will remain in a high impedance state. A high-to-low transition on the CS pin is required to start an operation, and a low-to-high tran- sition on the CS pin is required to end an operation. WRITE PROTECT: If the WP pin is held low, the first 256 pages of the main memory cannot be reprogrammed. The only way to reprogram the first 256 pages is to first drive the protect pin high and then use the program commands previously mentioned. The WP pin is internally pulled high; therefore, connection of the WP pin is not necessary if this pin and feature will not be utilized. However, it is recom- me nd ed tha t th e WP pin be driven high extern ally whenever possible. RESET: A low state on the reset pin (RESET) will terminate the operation in progress and reset the internal state machine to an idle state. The device will remain in the reset condition as long as a low level is present on the RESET pin. Normal operation can resume once the RESET pin is brought back to a high level. The device incorporates an internal power-on reset circuit, so there are no restrictions on the RESET pin during power-on sequences. The RESET pin is also internally pulled high; therefore, connection of the RESET pin is not necessary if this pin and feature will not be utilized. How- ever, it is recommended that the RESET pin be driven high externally whenever possible. READY/BUSY: This open drain output pin will be driven low when the device is busy in an internally self-timed oper- ation. This pin, which is normally in a high state (through a1k Ω external pull-up resistor), will be pulled low during programming operations, compare operations, and during page-to-buffer transfers. The busy status indicates that the Flash memory array and one of the buffers cannot be accessed; read and write operations to the other buffer can still be performed. Power-on/Reset State When power is first applied to the device, or when recover- ing from a reset condition, the device will default to SPI Mode 3. In addition, the SO pin will be in a high impedance state, and a high-to-low transition on the CS pin will be required to start a valid instruction. The SPI mode will be automatically selected on every falling edge of CS by sampling the inactive clock state. |
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