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NB7L86MMNR2 Datasheet(PDF) 9 Page - ON Semiconductor |
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NB7L86MMNR2 Datasheet(HTML) 9 Page - ON Semiconductor |
9 / 12 page NB7L86M http://onsemi.com 9 Q Q VCC 16 mA 50 W 50 W Figure 20. CML Output Structure VEE Table 10. INTERFACING OPTIONS INTERFACING OPTIONS CONNECTIONS CML Connect VTD0, VTD0, VTD1, VTD1, VTSEL to VCC LVDS Connect VTD0, VTD0 together for D0 input. Connect VTD1, VTD1 together for D0 input. Leave VTSEL open for SEL input. AC−COUPLED Bias VTD0, VTD0, VTSEL and VTD1, VTD1 Inputs within (VCMR) Common Mode Range RSECL, LVPECL Standard ECL Termination Techniques. See AND8020/D. LVTTL, LVCMOS An external voltage should be applied to the unused complementary differential input. Nominal voltage 1.5 V for LVTTL and VCC/2 for LVCMOS inputs. |
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Similar Description - NB7L86MMNR2 |
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