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NB4N840M Datasheet(PDF) 1 Page - ON Semiconductor |
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NB4N840M Datasheet(HTML) 1 Page - ON Semiconductor |
1 / 9 page © Semiconductor Components Industries, LLC, 2007 March, 2007 − Rev. 3 1 Publication Order Number: NB4N840M/D NB4N840M 3.3V 3.2Gb/s Dual Differential Clock/Data 2 x 2 Crosspoint Switch with CML Output and Internal Termination Description The NB4N840M is a high−bandwidth fully differential dual 2 x 2 crosspoint switch with CML inputs/outputs that is suitable for applications such as SDH/SONET, DWDM, Gigabit Ethernet and high speed switching. Fully differential design techniques are used to minimize jitter accumulation, crosstalk, and signal skew, which make this device ideal for loop−through and protection channel switching applications. Internally terminated differential CML inputs accept AC−coupled LVPECL (Positive ECL) or direct coupled CML signals. By providing internal 50 W input and output termination resistor, the need for external components is eliminated and interface reflections are minimized. Differential 16 mA CML outputs provide matching internal 50 W terminations, and 400 mV output swings when externally terminated, 50 W to VCC. Single−ended LVCMOS/LVTTL SEL inputs control the routing of the signals through the crosspoint switch which makes this device configurable as 1:2 fan−out, repeater or 2 x 2 crosspoint switch. The device is housed in a low profile 5 x 5 mm 32−pin QFN package. Features • Plug−in compatible to the MAX3840 and SY55859L • Maximum Input Clock Frequency 2.7 GHz • Maximum Input Data Frequency 3.2 Gb/s • 225 ps Typical Propagation Delay • 80 ps Typical Rise and Fall Times • 7 ps Channel to Channel Skew • 430 mW Power Consumption • < 0.5 ps RMS Jitter • 7 ps Peak−to−Peak Data Dependent Jitter • Power Saving Feature with Disabled Outputs • Operating Range: VCC = 3.0 V to 3.6 V with VEE = 0 V • CML Output Level (400 mV Peak−to−Peak Output), Differential Output • These are Pb−Free Devices QFN32 MN SUFFIX CASE 488AM See detailed ordering and shipping information on page 8 of this data sheet. ORDERING INFORMATION MARKING DIAGRAM http://onsemi.com 32 1 NB4N 840M ALYWG 1 A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week G = Pb−Free Package CML CML CML CML CML CML CML CML 0 1 0 1 0 1 0 1 Figure 1. Functional Block Diagram QA0 QA0 ENA0 SELA0 QA1 QA1 ENA1 SELA1 QB0 QB0 ENB0 SELB0 QB1 QB1 ENB1 SELB1 DA0 DA0 DA1 DA1 DB0 DB0 DB1 DB1 |
Similar Part No. - NB4N840M_07 |
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Similar Description - NB4N840M_07 |
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