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MC9S08RC60DWE Datasheet(PDF) 9 Page - Freescale Semiconductor, Inc

Part # MC9S08RC60DWE
Description  Microcontrollers
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MC9S08RC60DWE Datasheet(HTML) 9 Page - Freescale Semiconductor, Inc

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MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
Freescale Semiconductor
9
Section Number
Title
Page
5.8
Reset, Interrupt, and System Control Registers and Control Bits ...................................................64
5.8.1
Interrupt Pin Request Status and Control Register (IRQSC) .........................................64
5.8.2
System Reset Status Register (SRS) ...............................................................................65
5.8.3
System Background Debug Force Reset Register (SBDFR) ..........................................67
5.8.4
System Options Register (SOPT) ...................................................................................68
5.8.5
System Device Identification Register (SDIDH, SDIDL) ..............................................69
5.8.6
System Real-Time Interrupt Status and Control Register (SRTISC) .............................70
5.8.7
System Power Management Status and Control 1 Register (SPMSC1) .........................71
5.8.8
System Power Management Status and Control 2 Register (SPMSC2) .........................72
Chapter 6
Parallel Input/Output
6.1
Introduction .....................................................................................................................................73
6.2
Features ...........................................................................................................................................73
6.3
Pin Descriptions ..............................................................................................................................74
6.3.1
Port A ..............................................................................................................................74
6.3.2
Port B ..............................................................................................................................74
6.3.3
Port C ..............................................................................................................................75
6.3.4
Port D ..............................................................................................................................75
6.3.5
Port E ..............................................................................................................................76
6.4
Parallel I/O Controls ........................................................................................................................76
6.4.1
Data Direction Control ...................................................................................................76
6.4.2
Internal Pullup Control ...................................................................................................77
6.5
Stop Modes ......................................................................................................................................77
6.6
Parallel I/O Registers and Control Bits ...........................................................................................77
6.6.1
Port A Registers (PTAD, PTAPE, and PTADD) ............................................................78
6.6.2
Port B Registers (PTBD, PTBPE, and PTBDD) ............................................................79
6.6.3
Port C Registers (PTCD, PTCPE, and PTCDD) ............................................................81
6.6.4
Port D Registers (PTDD, PTDPE, and PTDDD) ...........................................................82
6.6.5
Port E Registers (PTED, PTEPE, and PTEDD) .............................................................84
Chapter 7
Central Processor Unit (S08CPUV2)
7.1
Introduction .....................................................................................................................................87
7.1.1
Features ...........................................................................................................................87
7.2
Programmer’s Model and CPU Registers .......................................................................................88
7.2.1
Accumulator (A) .............................................................................................................88
7.2.2
Index Register (H:X) ......................................................................................................88
7.2.3
Stack Pointer (SP) ...........................................................................................................89
7.2.4
Program Counter (PC) ....................................................................................................89
7.2.5
Condition Code Register (CCR) .....................................................................................89
7.3
Addressing Modes ...........................................................................................................................90
7.3.1
Inherent Addressing Mode (INH) ..................................................................................91
7.3.2
Relative Addressing Mode (REL) ..................................................................................91
7.3.3
Immediate Addressing Mode (IMM) .............................................................................91


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