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ZL50111GAG2 Datasheet(PDF) 11 Page - Zarlink Semiconductor Inc |
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ZL50111GAG2 Datasheet(HTML) 11 Page - Zarlink Semiconductor Inc |
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11 / 103 page  ZL50110/11/14 Data Sheet 11 Zarlink Semiconductor Inc. 1.0 Changes Summary The following table captures the changes from the February 2006 issue. The following table captures the changes from the April 2005 issue. The following table captures the changes from the January 2005 issue. The following table captures the changes from the October 2004 issue. The following table captures the changes from the September 2004 issue. Page Item Change 86 Table 38, Table 38 - External Memory Timing Added Minimum Values Page Item Change Clarified ZL50111 supports 3 MII ports, ZL50110/4 support 2 MII ports. 41, 42 Section 3.6 and Section 3.7.2 Added external pull-up/pull-down resistor recommendations for SYSTEM_RST, SYSTEM_DEBUG, JTAG_TRST, JTAG_TCK. 57 Section 6.3 Added Section 6.3 SYSTEM_CLK Considerations. Page Item Change Clarified data sheet to indicate ZL5011x supports clock recovery in both synchronous and asynchronous modes of operation. 89 Figure 44 Inverted polarity of CPU_DREQ0 and CPU_DREQ1 to conform with default MPC8260. Polarity of CPU_DREQ and CPU_SDACK remains programmable through API. 89 Figure 45 Inverted polarity of CPU_DREQ0 and CPU_DREQ1 to conform with default MPC8260. Polarity of CPU_DREQ and CPU_SDACK remains programmable through API. Page Item Change 42 Section 3.7.1 Added 5 kohm pulldown recommendation to GPIO signals. Page Item Change 12, 16, 19 Fig. 2 and Ball Signal Assignment Table Corrected Mx_LINKUP_LED pin assignment. 73 DC Electrical Characteristics Table and Output Levels Table Changed Electrical Characteristics to differentiate between 3.3 V and 5 V tolerant signals. 98 Section 13.3 New section added; Mx_LINKUP_LED Outputs. |
Similar Part No. - ZL50111GAG2 |
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Similar Description - ZL50111GAG2 |
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