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ZL50110 Datasheet(PDF) 1 Page - Zarlink Semiconductor Inc |
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ZL50110 Datasheet(HTML) 1 Page - Zarlink Semiconductor Inc |
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1 / 103 page  1 Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2003-2006, Zarlink Semiconductor Inc. All Rights Reserved. Features General • Circuit Emulation Services over Packet (CESoP) transport for MPLS, IP and Ethernet networks • On chip timing & synchronization recovery across a packet network • Grooming capability for Nx64 Kbps trunking Circuit Emulation Services • Complies with ITU-T recommendation Y.1413 • Complies with IETF PWE3 draft standards for CESoPSN and SAToP • Complies with CESoP draft IAs for MEF and MFA • Structured, synchronous CESoP with clock recovery • Unstructured, asynchronous CESoP, with integral per stream clock recovery TDM Interfaces • Up to 32 T1/E1, 8 J2, 2 T3/E3 or 1 STS-1 ports • H.110, H-MVIP, ST-BUS backplanes • Up to 1024 bi-directional 64 Kbps channels • Direct connection to LIUs, framers, backplanes • Dual reference Stratum 3, 4 and 4E DPLL for synchronous operation Network Interfaces • Up to 3 x 100 Mbps MII Fast Ethernet or Dual Redundant 1000 Mbps GMII/TBI Ethernet Interfaces System Interfaces • Flexible 32 bit host CPU interface (Motorola PowerQUICC™ compatible) • On-chip packet memory for self-contained operation, with buffer depths of over 16 ms • Up to 8 Mbytes of off-chip packet memory, supporting buffer depths of over 128 ms October 2006 Ordering Information ZL50110GAG 552 PBGA Trays, Bake & Drypack ZL50111GAG 552 PBGA Trays, Bake & Drypack ZL50114GAG 552 PBGA Trays, Bake & Drypack ZL50110GAG2 552 PBGA** Trays, Bake & Drypack ZL50111GAG2 552 PBGA** Trays, Bake & Drypack ZL50114GAG2 552 PBGA** Trays, Bake & Drypack **Pb Fee Tin Silver/Copper -40°C to +85°C ZL50110/11/14 128, 256 and 1024 Channel CESoP Processors Data Sheet Figure 1 - ZL50110/11/14 High Level Overview On Chip Packet Memory (Jitter Buffer Compensation for 16-128 ms of Packet Delay Variation) Dual Reference Stratum 3 DPLL Host Processor Interface External Memory Interface (optional) 32-bit Motorola compatible DMA for signaling packets Multi-Protocol Packet Processing Engine PW, RTP, UDP, IPv4, IPv6, MPLS, ECID, VLAN, User Defined, Others Triple Packet Interface MAC (MII, GMII, TBI) TDM Interface (LIU, Framer, Backplane) Per Port DCO for Clock Recovery ZBT-SRAM (0 - 8 Mbytes) |
Similar Part No. - ZL50110_06 |
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Similar Description - ZL50110_06 |
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