CAT9954HV4I-T2 datasheet(9/16 Pages) CATALYST

Part #	CAT9954HV4I-T2

Description	8-bit I2C and SMBus I/O Port with Interrupt

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Manufacturer	CATALYST [Catalyst Semiconductor]

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9 / 16 page

CAT9554, CAT9554A

9

Doc. No. 25088, Rev. B

Characteristics subject to change without notice

Figure 8. Acknowledge Timing

Acknowledge

After a successful data transfer, each receiving device

is required to generate an acknowledge. The

acknowledging device pulls down the SDA line during

the ninth clock cycle, signaling that it received the 8 bits

of data. The SDA line remains stable LOW during the

HIGH period of the acknowledge related clock pulse

(Figure 5).

The CAT9554/9554A respond with an acknowledge

after receiving a START condition and its slave address.

If the device has been selected along with a write

operation, it responds with an acknowledge after

receiving each 8-bit byte.

When the CAT9554/9554A begins a READ mode it

transmits 8 bits of data, releases the SDA line, and

monitors the line for an acknowledge. Once it receives

this acknowledge, the CAT9554/9554A will continue to

transmit data. If no acknowledge is sent by the Master,

the device terminates data transmission and waits for a

STOP condition. The master must then issue a STOP

condition to return the CAT9554/9554A to the standby

power mode and place the device in a known state.

Registers and Bus Transactions

The CAT9554/9554A consist of an input port register,

an output port register, a polarity inversion register and

a configuration register. Table 1 shows the register

address table. Tables 2 to 5 list Register 0 through

Register 3 information.

The command byte is the first byte to follow the device

address byte during a write/read bus transaction. The

register command byte acts as a pointer to determine

which register will be written or read.

The input port register is a read only port. It reflects the

incoming logic levels of the I/O pins, regardless of

whether the pin is defined as an input or an output by the

configuration register. Writes to the input port register

are ignored.

18

9

START

SCL FROM

MASTER

BUS RELEASE DELAY (TRANSMITTER)

ACK DELAY

ACK SETUP

BUS RELEASE DELAY (RECEIVER)

DATA OUTPUT

FROM TRANSMITTER

DATA OUTPUT

FROM RECEIVER

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Table 1. Register Command Byte

Table 3. Register 1 – Output Port Register

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7

I6

I5

I4

I3

I2

I1

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1111

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1111

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Table 2. Register 0 – Input Port Register

Table 4. Register 2 – Polarity Inversion Register

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N6

N5

N4

N3

N2

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Table 5. Register 3 – Configuration Register

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