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ELECTRICAL CHARACTERISTICS

PCM3002

PCM3003

SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated

circuits be handled with appropriate precautions. Failure to observe proper handling and installation

procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision

integrated circuits may be more susceptible to damage because very small parametric changes could

cause the device not to meet its published specifications.

All specifications at T

PCM3002E/3003E

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

DIGITAL INPUT/OUTPUT

Input Logic

Input logic level

VDC

±1

Input logic current

µA

100

Output Logic

Output logic level

0.3

VDC

0.3

CLOCK FREQUENCY

Sampling frequency

44.1

48

kHz

1.024

11.2896

12.288

System clock frequency

1.536

16.9344

18.432

MHz

2.048

22.5792

24.576

ADC CHARACTERISTICS

Resolution

20

Bits

DC Accuracy

Gain mismatch, channel-

±1

±3

% of FSR

to-channel

Gain error

±2

±5

% of FSR

Gain drift

±20

ppm of FSR/

°C

Bipolar zero error

±1.7

% of FSR

Bipolar zero drift

±20

ppm of FSR/

°C

–86

–80

THD+N

dB

–28

Dynamic range

A-weighted

86

90

dB

Signal-to-noise ratio

A-weighted

86

90

dB

Channel separation

84

88

dB

(1)

Pins 7, 8, 17 and 18: RST, ML, MD, and MC for the PCM3002; PDAD, PDDA, DEM1, and DEM0 for PCM3003 (Schmitt-trigger input

with 100-k

Ω typical internal pulldown resistor)

(2)

Pins 9, 10, 11, 15: SYSCLK, LRCIN, BCKIN, DIN (Schmitt-trigger input)

(3)

Pin 16: 20BIT for PCM3003 (Schmitt-trigger input, 100-k

Ω typical internal pulldown resistor)

(4)

Pin 12: DOUT

(5)

Pin 16: ZFLG for PCM3002 (open-drain output)

(6)

See Application Bulletin SBAA033 for information relating to operation at lower sampling frequencies.

(7)

High-pass filter for offset cancel

(8)

for performance calculation.

2