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CAT28LV256PI-30T Datasheet(PDF) 5 Page - Catalyst Semiconductor |
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CAT28LV256PI-30T Datasheet(HTML) 5 Page - Catalyst Semiconductor |
5 / 12 page CAT28LV256 5 Doc. No. 1071, Rev. B A.C. CHARACTERISTICS, Write Cycle VCC = 3.0V to 3.6V, unless otherwise specified 28LV256-20 28LV256-25 28LV256-30 Symbol Parameter Min. Max. Min. Max. Min. Max. Units tWC Write Cycle Time 10 10 10 ms tAS Address Setup Time 0 0 0 ns tAH Address Hold Time 100 100 100 ns tCS CE Setup Time 0 0 0 ns tCH CE Hold Time 0 0 0 ns tCW(3) CE Pulse Time 150 150 150 ns tOES OE Setup Time 0 0 0 ns tOEH OE Hold Time 0 0 0 ns tWP(3) WE Pulse Width 150 150 150 ns tDS Data Setup Time 50 50 50 ns tDH Data Hold Time 0 0 0 ns tINIT(1) Write Inhibit Period After Power-up 5 10 5 10 5 10 ms tBLC(1)(4) Byte Load Cycle Time 0.15 100 0.15 100 0.15 100 µs Vcc 1.8K CL = 100 pF CL INCLUDES JIG CAPACITANCE 1.3K DEVICE UNDER TEST OUTPUT INPUT PULSE LEVELS REFERENCE POINTS 2.0 V 0.6 V VCC - 0.3V 0.0 V Figure 1. A.C. Testing Input/Output Waveform(2) 28LV256 F04 Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) Input rise and fall times (10% and 90%) < 10 ns. (3) A write pulse of less than 20ns duration will not initiate a write cycle. (4) A timer of duration tBLC max. begins with every LOW to HIGH transition of WE. If allowed to time out, a page or byte write will begin; however a transition from HIGH to LOW within tBLC max. stops the timer. Figure 2. A.C. Testing Load Circuit (example) 28LV256 F05 |
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