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CAT34RC02VP2ITE13 Datasheet(PDF) 7 Page - Catalyst Semiconductor |
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CAT34RC02VP2ITE13 Datasheet(HTML) 7 Page - Catalyst Semiconductor |
7 / 14 page Discontinued Part CAT34RC02 7 Doc No. 1052, Rev. O © 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice The PSWP flag can be set (forever) by issuing a ‘Byte Write’ command, with the Slave address preamble set to ‘6h’, followed by a ‘don’t care’ address, followed by ‘don’t care’ data and a STOP condition. The CAT34RC02 will acknowledge the Slave address, dummy byte address and dummy data (Fig. 10). The PSWP flag will be permanently set (after the internal write cycle is completed). The SWP commands are shown in Table 1. Table 1. SWP Commands s s e r d d A e v a l S N I Pe l b m a e r Ps s e r d d A e c i v e DR/ W W W W W d n a m m o C2 A1 A0 A7 B6 B5 B4 B3 B2 B1 B0 B P W S D A E R 2 A1 A0 A0 1 1 0 2 A1 A0 A1 T E S P W S R0 0 V H V0 1 1 0 0 0 1 0 P W S R R A E L C 01 V H V0 1 1 0 0 1 1 0 T E S P W S P2 A1 A0 A0 1 1 0 2 A1 A0 A0 The CAT34RC02 will not acknowledge RSWP or PSWP commands, once the PSWP flag is set. If the PSWP flag is not set, but the WP pin is HIGH, then the CAT34RC02 will react to RSWP or PSWP commands as follows: if the command attempts to ‘flip’ one of the two SWP switches, then the CAT34RC02 will respond the same way the regular memory would, i.e. the command and address (in this case dummy) are acknowledged, but the data (in this case dummy) will not be acknowledged; if the command attempts to ‘reaffirm’ one of the two switches, then the CAT34RC02 will not acknowledge the command itself. In addition, the CAT34RC02 will not acknowledge a ‘reaffirming’ SWP command, even if the WP pin is LOW. Power-On Reset (POR) The CAT34RC02 incorporates Power-On Reset (POR) circuitry which protects the device against malfunctioning while VCC is lower than the recommended operating voltage. The device will power up into a read-only state and will power-down into a reset state when VCC crosses the POR level of ~1.3V. READ OPERATIONS Immediate Address Read In standby mode, the CAT34RC02 internal address counter points to the data byte immediately following the last byte accessed by a previous operation. If the ‘previous’ byte was the last byte in memory, then the address counter will point to the first memory byte, etc. If the CAT34RC02 decodes a Slave address with a ‘1’ in the R/ W bit position (Fig. 8), it will issue an ACK in the 9th clock cycle, and will then transmit the data byte being pointed at by the address counter. The Master can then stop further transmission by issuing a NoACK, followed by a STOP condition. Selective Read The READ operation can also be started at an address different from the one stored in the address counter. The Figure 8. Immediate Address Read Timing SCL SDA 8th Bit STOP NO ACK DATA OUT 89 SLAVE ADDRESS S A C K DATA N O A C K S T O P P BUS ACTIVITY: MASTER SDA LINE S T A R T |
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