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MC100EPT26DR2G Datasheet(PDF) 1 Page - ON Semiconductor |
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MC100EPT26DR2G Datasheet(HTML) 1 Page - ON Semiconductor |
1 / 9 page © Semiconductor Components Industries, LLC, 2006 November, 2006 − Rev. 14 1 Publication Order Number: MC100EPT26/D MC100EPT26 3.3V1:2 Fanout Differential LVPECL/LVDS to LVTTL Translator Description The MC100EPT26 is a 1:2 Fanout Differential LVPECL/LVDS to LVTTL translator. Because LVPECL (Positive ECL) or LVDS levels are used only +3.3 V and ground are required. The small outline 8−lead package and the 1:2 fanout design of the EPT26 makes it ideal for applications which require the low skew duplication of a signal in a tightly packed PC board. The VBB output allows the EPT26 to be used in a single−ended input mode. In this mode the VBB output is tied to the D0 input for a non−inverting buffer or the D0 input for an inverting buffer. If used, the VBB pin should be bypassed to ground with > 0.01 mF capacitor. For a single−ended direct connection, use an external voltage reference source such as a resistor divider. Do not use VBB for a single−ended direct connection or port to another device. Features • 1.4 ns Typical Propagation Delay • Maximum Frequency > 275 MHz Typical • The 100 Series Contains Temperature Compensation • Operating Range: VCC = 3.0 V to 3.6 V with GND = 0 V • 24 mA TTL outputs • Q Outputs Will Default LOW with Inputs Open or at VEE • VBB Output • Pb−Free Packages are Available *For additional marking information, refer to Application Note AND8002/D. MARKING DIAGRAMS* A = Assembly Location L = Wafer Lot Y = Year W = Work Week M = Date Code G = Pb−Free Package ALYWG G KA26 SO−8 D SUFFIX CASE 751 1 8 TSSOP−8 DT SUFFIX CASE 948R 1 8 1 8 See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. ORDERING INFORMATION KPT26 ALYW G 1 8 http://onsemi.com DFN8 MN SUFFIX CASE 506AA 3W MG G 1 4 (Note: Microdot may be in either location) |
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