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CAT40C00UITE13 Datasheet(PDF) 6 Page - Catalyst Semiconductor |
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CAT40C00UITE13 Datasheet(HTML) 6 Page - Catalyst Semiconductor |
6 / 10 page Discontinued Part CAT24C00 6 Doc. No. 1027, Rev. O © 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice bits are transmitted before the stop bit is sent, then the device will clear the previously loaded byte and begin loading the data buffer again. If more than one data byte is transmitted to the device and a stop bit is sent before a full eight bits of data have been transmitted, then the write command will abort and no data will be written. Acknowledge Polling The disabling of the inputs can be used to take advantage of the typical write cycle time. Once the stop condition is issued to indicate the end of the host’s write operation, the CAT24C00 initiates the internal write cycle. ACK polling can be initiated immediately. This involves issuing the start condition followed by the slave address for a write operation. If the CAT24C00 is still busy with the write operation, no ACK will be returned. If the CAT24C00 has completed the write operation, an ACK will be returned and the host can then proceed with the next read or write operation. READ OPERATIONS The READ operation for the CAT24C00 is initiated in the same manner as the write operation with the one exception that the R/ W bit is set to a one. Three different READ operations are possible: Immediate Address READ, Selective READ and Sequential READ. Immediate Address Read The device’s address counter contains the address of the last byte accessed, incremented by one. In other words, if the last READ access was to address N, the READ immediately following would access data from address N+1. If N=15, then the counter will 'wrap around' to address 0 and continue to clock out data. Figure 5. Slave Address Bits 1 0 1 0 X X X R/W CAT24C00 Selective Read Selective READ operations allow the Master device to select at random any memory location for a READ operation. The Master device first performs a ‘dummy’ write operation by sending the START condition, slave address and byte address of the location it wishes to read. After the CAT24C00 acknowledges the word address, the Master device resends the START condition and the slave address, this time with the R/ W bit is set to one. The CAT24C00 then responds with its acknowledge and sends the 8-bit byte requested. To end the Read Operation the master device does not send an acknowledge but will generate a STOP condition. Sequential Read The Sequential READ operation can be initiated by either the immediate Address READ or Selective READ operations. After the CAT24C00 sends initial 8-bit byte requested, the Master will respond with an acknowledge which tells the device it requires more data. The CAT24C00 will continue to output an 8-bit byte for each acknowledge sent by the Master. The operation is terminated when the Master fails to respond with an acknowledge, thus sending the STOP condition. The data being transmitted from the CAT24C00 is outputted sequentially with data from address N followed by data from address N+1. The READ operation address counter increments all of the CAT24C00 address bits so that the entire memory array can be read during one operation. If more than 16 bytes are read out, the counter will “wrap around” and continue to clock out data bytes. |
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