CAT24C256

3

Doc No. 04, Rev. D

© 2007 by Catalyst Semiconductor, Inc.

Characteristics subject to change without notice

Symbol

Parameter

1.8 V - 5.5 V

2.5 V - 5.5 V

units

Min

Max

Min

Max

Clock Frequency

00

400

kHz

Noise Suppression Time Constant at

SCL, SDA Inputs

0.

0.

µs

SCL Low to SDA Data Out

3.5

0.9

µs

Time the Bus Must be Free Before a

New Transmission Can Start

4.7

.3

µs

Start Condition Hold Time

4

0.6

µs

Clock Low Period

4.7

.3

µs

Clock High Period

4

0.6

µs

Start Condition Setup Time

4.7

0.6

µs

Data In Hold Time

0

0

µs

Data In Setup Time

0.25

0.

µs

SDA and SCL Rise Time



0.3

µs

SDA and SCL Fall Time

0.3

0.3

µs

Stop Condition Setup Time

4

0.6

µs

Data Out Hold Time

0.

0.

µs

Write Cycle Time

5

5

ms

Power-up to Ready Mode





ms

notes:

() Test conditions according to “A.C. Test Conditions” table.

(2) Tested initially and after a design or process change that affects this parameter.

A.C. TEST COnDITIOnS

Input Levels

Input Reference Levels

Output Reference Levels

Output Load