CC1050SK datasheet(5/40 Pages) TI

Part #	CC1050SK

Description	Single Chip Very Low Power RF Transmitter

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CC1050

SWRS044

Page 5 of 40

Parameter

Min.

Typ.

Max.

Unit

Condition / Note

Spurious emission

-36

dBm

Complies with EN 300 220

Harmonics

-20

dBc

An external LC should be used to

reduce harmonics emission to

comply with SRD requirements.

See p.27.

Frequency Synthesiser

Section

Crystal Oscillator Frequency

3

16

MHz

Crystal frequency can be 3-4, 6-8

or 9-16 MHz. Recommended

frequencies are 3.6864, 7.3728,

11.0592 and 14.7456. See page

26 for details.

Crystal frequency accuracy

requirement

± 50

± 25

ppm

433 MHz

868 MHz

The crystal frequency accuracy

and drift (ageing and

temperature dependency) will

determine the frequency accuracy

of the transmitted signal.

Crystal operation

Parallel

C3 and C4 are loading

capacitors, see page 26

Crystal load capacitance

12

22

16

30

16

pF

3-8 MHz, 22 pF recommended

6-8 MHz, 16 pF recommended

9-16 MHz, 16 pF recommended

Crystal oscillator start-up time

4

1.5

2

ms

3.6864 MHz, 16 pF load

7.3728 MHz, 16 pF load

16 MHz, 16 pF load

Output signal phase noise

-80

dBc/Hz

At 100 kHz offset from carrier

PLL lock time

200

µs

Up to 1 MHz frequency step

PLL turn-on time, crystal oscillator

on in power down mode

250

µs

Crystal oscillator running

Digital Inputs/Outputs

Logic "0" input voltage

0

0.3*VDD

V

Logic "1" input voltage

0.7*VDD

VDD

V

Logic "0" output voltage

0

0.4

V

Output current -2.5 mA,

3.0 V supply voltage

Logic "1" output voltage

2.5

VDD

V

Output current 2.5 mA,

3.0 V supply voltage

Logic "0" input current

NA

-1

µA

Input signal equals GND

Logic "1" input current

NA

1

µA

Input signal equals VDD

DI setup time

20

ns

TX mode, minimum time DI must

be ready before the positive edge

of DCLK

DI hold time

10

ns

TX mode, minimum time DI must

be held after the positive edge of

DCLK

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