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SP8855E Datasheet(PDF) 10 Page - Zarlink Semiconductor Inc

Part # SP8855E
Description  2.8GHz Parallel Load Professional Synthesiser
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Manufacturer  ZARLINK [Zarlink Semiconductor Inc]
Direct Link  http://www.zarlink.com
Logo ZARLINK - Zarlink Semiconductor Inc

SP8855E Datasheet(HTML) 10 Page - Zarlink Semiconductor Inc

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10
SP8855E Advance Information
If a faster indication is required, comparable with the loop
lock up time, the capacitor will need to be 2-3 times smaller
than the time constant calculation suggests. The time to
respond to an out of lock conditions is 2-3 times less than that
required to indicate lock.
Charge pump circuit
The charge pump circuit converts the variable width up and
down pulses from the phase detector into adjustable current
pulses which can be directly connected to the loop amplifier.
The magnitude of the current and therefore the phase detector
gain can be modified when new frequency data is entered to
compensate for change in the VCO gain characteristics over
its frequency band. The charge pump pulse current is
determined by the current fed into pin 19 and is approximately
equal to pin 19 current when the programmed multiplication
ratio is one. The circuit diagram Fig. 7e shows the internal
components on pin 19 which mirror the input current into the
charge pump. The voltage at pin 19 will be approximately 1.6V
above ground due to two V
be drops in the current mirror. This
voltage will exhibit a negative temperature coefficient, causing
the charge pump current to change with chip temperature by
up to 10% over the full military temperature range if the current
programming resistor is connected to V
CC as shown in the
application diagram Fig. 5. In critical applications where this
change in charge pump current would be too large the resistor
to pin 19 could be increased in value and connected to a higher
supply to reduce the effect of V
be
variation on the current level.
A suitable resistor connected to a 30V supply would reduce
the variation in pin 19 current due to temperature to less than
1.5%. Alternatively a stable current source could be used to
set pin 19 current.
The charge pump output on pin 20 will only produce
symmetrical up and down currents if the voltage is equal to that
on the voltage reference pin 21. In order to ensure that this
voltage relationship is maintained, an operational amplifier
must be used as shown in the typical application Fig. 5. Using
this configuration pin 20 voltage will be forced to be equal to
that pin 21 since the operational amplifier differential input
voltage will be no more than a few millivolts (the input offset
voltage of the amplifier). When the synthesiser is first switched
on or when a frequency outside VCO range is programmed the
amplifier output will limit, allowing pin 20 voltage to differ from
that on pin 21. As soon as an achievable frequency value is
programmed and the amplifier output starts to slew the correct
voltage relationship between pin 20 and 21 will be restored.
Because of the importance of voltage equality between the
charge pump reference and output pins, a resistor should
never be connected in series with the operational amplifier
inverting input and pin 20 as is the case with a phase detector
giving voltage outputs. Any current drawn from the charge
pump reference pin should be limited to the few micro amps
input current of a typical operational amplifier. A resistor
between the charge pump reference and the non inverting
input could be added to provide isolation but the value should
not be so high that more than a few millivolts drop are
produced by the amplifier input current.
When selecting a suitable amplifier for the loop filter, a
number of parameters are important; input offset voltage in
most designs is only a few millivolts and an offset of 5mV will
produce a mismatch in the up and down currents of about 4%
with the charge pump multiplication factor set at 1. The
mismatch in up down currents caused by input offset voltage
will be reduced in proportion to the charge pump multiplication
factor in use. If the linearity of the phase detector about the
normal phase locked operating point is critical, the input offset
voltage of most amplifiers can be adjusted to near zero by
means of a potentiometer.
The charge pump reference voltage on pin 21 is about 1.3V
below the positive supply and will change with the temperature
and with the programmed charge pump multiplication factor.
In many cases it is convenient to operate the amplifier with the
negative power supply pin connected to 0V as this removes
the need for an additional power supply. The amplifier
selected must have a common mode range to within 3.4V
(minimum charge pump reference voltage) of the negative
supply pin to operate correctly without a negative supply. Most
popular amplifiers can be operated from a 30V positive supply
to give a wide VCO voltage drive range and have adequate
common mode range to operate with inputs at +3.4V with
respect to the negative supply. Input bias and offset current
levels to most operational amplifiers are unlikely to be high
enough to significantly affect the accuracy of the charge pump
circuit currents but the bias current can be important in
reducing reference side bands and local oscillator drift during
frequency changes. When the loop is locked, the charge pump
produces only very narrow pulses of sufficient width to make
up for any charge lost from the loop filter components during
the reference cycle. The charge lost will be due to leakage
from the charge pump output pin and to the amplifier input
bias current the latter usually being more significant. The
result of the lost charge is a sawtooth ripple on the VCO control
line which frequency modulates the phase locked oscillator at
the reference frequency and its harmonics.
It is possible to disable the charge pump by taking pin 39
low. In this case any leakage current will cause the oscillator
to drift off frequency. This feature may be useful where having
achieved lock an external phase detector of the user's choice
can be employed to suit a specific application.
F
pd and Fref outputs
These outputs provide access to the outputs from the RF
and reference dividers and are provided for monitoring
purposes during product development or test, and for
connection of an external phase detector if required. The
output circuit is of ECL type, the circuit diagram being shown
in Fig. 7g. The outputs are enabled when pin 22 is high and
disabled when pin22 is low, but are best left in the disabled
state when not required as the fast edge speeds on the output
can increase the level of reference sidebands on the
synthesised oscillator.
The emitter follower outputs have no internal pull down
resistor to save current and if the outputs are required an
external pull down resistor should be fitted. The value should
be kept as high as possible to reduce supply current, about
2.2k. being suitable for monitoring with a high impedance
oscilloscope probe or for driving an AC coupled 50 Ohm load.


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