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MC74VHCT138ADR2 Datasheet(PDF) 1 Page - ON Semiconductor

Part # MC74VHCT138ADR2
Description  3?뭪o?? Line Decoder
Download  7 Pages
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Manufacturer  ONSEMI [ON Semiconductor]
Direct Link  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

MC74VHCT138ADR2 Datasheet(HTML) 1 Page - ON Semiconductor

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© Semiconductor Components Industries, LLC, 2006
January, 2006 − Rev. 3
1
Publication Order Number:
MC74VHCT138A/D
MC74VHCT138A
3−to−8 Line Decoder
The MC74VHCT138A is an advanced high speed CMOS 3−to−8
decoder fabricated with silicon gate CMOS technology. It achieves
high speed operation similar to equivalent Bipolar Schottky TTL
while maintaining CMOS low power dissipation.
When the device is enabled, three Binary Select inputs (A0 − A2)
determine which one of the outputs (Y0 − Y7) will go Low. When
enable input E3 is held Low or either E2 or E1 is held High, decoding
function is inhibited and all outputs go high. E3, E2, and E1 inputs are
provided to ease cascade connection and for use as an address decoder
for memory systems.
The VHCT inputs are compatible with TTL levels. This device can
be used as a level converter for interfacing 3.3 V to 5.0 V, because they
have full 5.0 V CMOS level output swings.
The VHCT138A input structures provide protection when voltages
between 0 V and 5.5 V are applied, regardless of the supply voltage.
The output structures also provide protection when VCC = 0 V. These
input and output structures help prevent device destruction caused by
supply voltage − input/output voltage mismatch, battery backup, hot
insertion, etc.
Features
High Speed: tPD = 7.6 ns (Typ) at VCC = 5.0 V
Low Power Dissipation: ICC = 4 mA (Max) at TA = 25°C
TTL−Compatible Inputs: VIL = 0.8 V; VIH = 2.0 V
Power Down Protection Provided on Inputs and Outputs
Balanced Propagation Delays
Designed for 4.5 V to 5.5 V Operating Range
Pin and Function Compatible with Other Standard Logic Families
Latchup Performance Exceeds 300 mA
ESD Performance:
Human Body Model > 2000 V;
Machine Model > 200 V
Chip Complexity: 122 FETs or 30.5 Equivalent Gates
Pb−Free Packages are Available*
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
MARKING
DIAGRAMS
TSSOP−16
DT SUFFIX
CASE 948F
SOIC−16
D SUFFIX
CASE 751B
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
ORDERING INFORMATION
http://onsemi.com
A
= Assembly Location
WL, L
= Wafer Lot
Y
= Year
WW, W
= Work Week
G or
G
= Pb−Free Package
VHCT138AG
AWLYWW
VHCT
138A
ALYW
G
G
(Note: Microdot may be in either location)
PIN ASSIGNMENT
13
14
15
16
9
10
11
12
5
4
3
2
1
8
7
6
A0
E1
A2
A1
Y7
E3
E2
GND
Y3
Y2
Y1
Y0
VCC
Y5
Y4
Y6
1
1
16
1
1
16


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