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MC74VHCT08ADTR2 Datasheet(PDF) 1 Page - ON Semiconductor

Part # MC74VHCT08ADTR2
Description  Quad 2?묲nput AND Gate
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Manufacturer  ONSEMI [ON Semiconductor]
Direct Link  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

MC74VHCT08ADTR2 Datasheet(HTML) 1 Page - ON Semiconductor

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© Semiconductor Components Industries, LLC, 2006
March, 2006 − Rev. 5
1
Publication Order Number:
MC74VHCT08A/D
MC74VHCT08A
Quad 2−Input AND Gate
The MC74VHCT08A is an advanced high speed CMOS 2−input
AND gate fabricated with silicon gate CMOS technology. It achieves
high speed operation similar to equivalent Bipolar Schottky TTL
while maintaining CMOS low power dissipation.
The VHCT inputs are compatible with TTL levels. This device can
be used as a level converter for interfacing 3.3 V to 5.0 V, because it
has full 5.0 V CMOS level output swings.
The VHCT08A input structures provide protection when voltages
between 0 V and 5.5 V are applied, regardless of the supply voltage.
The output structures also provide protection when VCC = 0 V. These
input and output structures help prevent device destruction caused by
supply voltage − input/output voltage mismatch, battery backup, hot
insertion, etc.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output. The
inputs tolerate voltages up to 7.0 V, allowing the interface of 5.0 V
systems to 3.0 V systems.
Features
High Speed: tPD = 4.3 ns (Typ) at VCC = 5 V
Low Power Dissipation: ICC = 2 mA (Max) at TA = 25°C
TTL−Compatible Inputs: VIL = 0.8 V; VIH = 2.0 V
Power Down Protection Provided on Inputs
Balanced Propagation Delays
Designed for 2 V to 5.5 V Operating Range
Low Noise: VOLP = 0.8 V (Max)
Pin and Function Compatible with Other Standard Logic Families
Latchup Performance Exceeds 300 mA
ESD Performance: Human Body Model; > 2000 V,
Machine Model; > 200 V
Chip Complexity: 24 FETs or 6 Equivalent Gates
Pb−Free Packages are Available*
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
http://onsemi.com
MARKING
DIAGRAMS
TSSOP−14
DT SUFFIX
CASE 948G
1
SOEIAJ−14
M SUFFIX
CASE 965
SOIC−14
D SUFFIX
CASE 751A
1
1
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
ORDERING INFORMATION
A
= Assembly Location
WL, L
= Wafer Lot
Y, YY
= Year
WW, W = Work Week
G or
G
= Pb−Free Package
1
14
VHCT08
ALYWG
VHCT08AG
AWLYWW
1
14
VHCT
08A
ALYW
G
G
1
14
(Note: Microdot may be in either location)


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