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MC100EP210S_06 Datasheet(PDF) 2 Page - ON Semiconductor

Part No. MC100EP210S_06
Description  2.5V 1:5 Dual Differential LVDS Compatible Clock Driver
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Maker  ONSEMI [ON Semiconductor]
Homepage  http://www.onsemi.com
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MC100EP210S
http://onsemi.com
2
CLKn, CLKn
LVDS, LVPECL CLK Inputs*
VCC
25
26
27
28
29
30
31
32
15
14
13
12
11
10
9
1
2345678
24
23
22
21
20
19
18
17
16
Qb4
Qb4
Qb3
Qb3
Qb2
Qb2
VCC
VCC
Qa0
Qa0
Qa1
Qa1
Qa2
Qa2
VCC
VEE
VTB
VEE
Qb1
Qb1
Qb0
Qb0
Qa4
Qa4
Qa3 Qa3
Qa0
Qa0
Qa1
Qa1
Qa2
Qa2
Qa3
Qa3
Qa4
Qa4
CLKa
CLKa
VTA
Qb0
Qb0
Qb1
Qb1
Qb2
Qb2
Qb3
Qb3
Qb4
Qb4
CLKb
CLKb
Warning: All VCC and VEE pins must be externally connected
to Power Supply to guarantee proper operation.
Table 1. PIN DESCRIPTION
PIN
Qn0:4, Qn0:4
LVDS Outputs
FUNCTION
VCC
Positive Supply
VEE
Ground
Figure 1. 32−Lead LQFP Pinout (Top View)
Figure 2. Logic Diagram
VTA
VTB
VTA
50
W
50
W
VTB
50
W
50
W
50
W Termination Resistors
50
W Termination Resistors
MC100EP210S
*Under open or floating conditions with input pins converging to a common termination
bias voltage the device is susceptible to auto oscillation.
VCC
25
26
27
28
29
30
31
32
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
16
Qb4 Qb4 Qb3 Qb3 Qb2 Qb2 VCC
VCC Qa0 Qa0 Qa1 Qa1 Qa2 Qa2 VCC
VEE
VTB
VEE
Qb1
Qb1
Qb0
Qb0
Qa4
Qa4
Qa3
Qa3
CLKa
CLKa
CLKb
CLKb
VTA
MC100EP210S
Figure 1. 32−Lead QFN Pinout (Top View)
The Exposed Pad (EP) on the QFN−32 package bottom is
thermally connected to the die for improved heat transfer out
of package. The exposed pad must be attached to a heat−
sinking conduit. The pad is electrically connected to VEE.
EP for QFN−32,
only




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