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MC100ELT23_06 Datasheet(PDF) 1 Page - ON Semiconductor

Part No. MC100ELT23_06
Description  5 V Dual Differential PECL to TTL Translator
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Maker  ONSEMI [ON Semiconductor]
Homepage  http://www.onsemi.com
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© Semiconductor Components Industries, LLC, 2006
December, 2006 − Rev. 14
1
Publication Order Number:
MC100ELT23/D
MC100ELT23
5 VDual Differential PECL
to TTL Translator
Description
The MC100ELT23 is a dual differential PECL to TTL translator.
Because PECL (Positive ECL) levels are used, only +5 V and ground
are required. The small outline 8-lead package and the dual gate
design of the ELT23 makes it ideal for applications which require the
translation of a clock and a data signal.
The PECL inputs are differential; therefore, the MC100ELT23 can
accept any standard differential PECL input referenced from a VCC of
5.0 V.
Features
3.5 ns Typical Propagation Delay
24 mA TTL Outputs
Flow Through Pinouts
The 100 Series Contains Temperature Compensation
Operating Range VCC = 4.75 V to 5.25 V with GND = 0 V
Internal Input 50 KW Pulldown Resistors
Q Output Will Default LOW with Inputs Left Open or < 1.3 V
Pb−Free Packages are Available
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
M
= Date Code
G
= Pb−Free Package
SOIC−8
D SUFFIX
CASE 751
MARKING DIAGRAMS*
TSSOP−8
DT SUFFIX
CASE 948R
ALYWG
G
KT23
1
8
1
8
http://onsemi.com
*For additional marking information, refer to
Application Note AND8002/D.
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
ORDERING INFORMATION
1
8
KLT23
ALYW
G
1
8
DFN8
MN SUFFIX
CASE 506AA
14
(Note: Microdot may be in either location)




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