MC74LVX540MELG datasheet(4/8 Pages) ONSEMI

Part #	MC74LVX540MELG

Description	Octal Bus Buffer Inverting

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MC74LVX540

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DC ELECTRICAL CHARACTERISTICS

VCC

TA = 25°C

TA = − 40 to 85°C

Symbol

Parameter

Test Conditions

VCC

V

Min

Typ

Max

Min

Max

Unit

VIH

Minimum High−Level Input Voltage

2.0

3.0

3.6

1.50

2.0

2.4

1.50

2.0

2.4

V

VIL

Maximum Low−Level Input Voltage

2.0

3.0

3.6

0.50

0.80

0.50

0.80

V

VOH

Minimum High−Level Output Voltage

Vi =VIH or VIL

IOH = − 50 mA

IOH =50 mA

2.0

30

1.9

29

2.0

30

1.9

29

V

Vin = VIH or VIL

IOH = − 50 mA

IOH = − 4 mA

3.0

2.9

2.58

3.0

2.9

2.48

VOL

Maximum Low−Level Output Voltage

Vi =VIH or VIL

IOL = 50 mA

IOL =50 mA

2.0

30

0.0

00

0.1

01

0.1

01

V

Vin = VIH or VIL

IOL = 50 mA

IOL = 4 mA

3.0

0.0

0.1

0.36

0.1

0.44

Iin

Maximum Input Leakage Current

Vin = 5.5 V or GND

0 to

3.6

$0.

1

$1.0

mA

IOZ

Maximum 3−State Leakage Current

Vin = VIL or VIH

Vout = VCC or GND

3.6

$0.

25

$2.5

mA

ICC

Maximum Quiescent Supply Current

Vin = VCC or GND

3.6

4.0

40.0

mA

AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0 ns)

TA = 25°C

TA = − 40 to 85°C

Symbol

Parameter

Test Conditions

Min

Typ

Max

Min

Max

Unit

tPLH,

tPHL

Maximum Propagation Delay,

A to Y

(Figures 4 and 6)

VCC = 2.7 V

CL = 15 pF

CL = 50 pF

6.2

8.5

11.3

14.9

1.0

13.5

17.0

ns

(Figures 4 and 6)

VCC = 3.3 ± 0.3 V

CL = 15 pF

CL = 50 pF

5.0

6.8

7.0

10.5

1.0

8.5

12.0

tPZL,

tPZH

Output Enable TIme,

OEn to Y

(Figures 5 and 7)

VCC = 2.7 V

CL = 15 pF

RL = 1 kW

CL = 50 pF

9.5

11.2

13.8

17.3

1.0

16.5

20.0

ns

(Figures 5 and 7)

VCC = 3.3 $ 0.3 V

CL = 15 pF

RL = 1k W

CL = 50 pF

7.0

8.8

10.5

14.0

1.0

12.5

16.0

tPLZ,

tPHZ

Output Disable Time,

OEn to Y

(Figures 5 and 7)

VCC = 2.7 V

CL = 50 pF

RL = 1 kW

9.8

17.9

1.0

20.0

ns

(Figures 5 and 7)

VCC = 3.3 ± 0.3 V

CL = 50 pF

RL = 1 kW

8.7

15.4

1.0

17.5

tOSLH,

tOSHL

Output to Output Skew

VCC = 2.7 V

CL = 50 pF

(Note 1)

1.5

ns

VCC = 3.3 $ 0.3 V

CL = 50 pF

(Note 1)

1.5

ns

Cin

Maximum Input Capacitance

4

10

pF

Cout

Maximum Three−State Output

Capacitance (Output in High

Impedance State)

6

pF

Typical @ 25

°C, VCC = 5.0 V

CPD

Power Dissipation Capacitance (Note 2)

17

pF

1. Parameter guaranteed by design. tOSLH = |tPLHm − tPLHn|, tOSHL = |tPHLm − tPHLn|.

2. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.

Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC / 8 (per bit). CPD is used to determine the no−load

dynamic power consumption; PD = CPD VCC2 fin + ICC VCC.

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