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MC74LVX259DR2G Datasheet(PDF) 5 Page - ON Semiconductor

Part # MC74LVX259DR2G
Description  8-Bit Addressable Latch/1-of-8 Decoder CMOS Logic Level Shifter with LSTTL?묬ompatible Inputs
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Manufacturer  ONSEMI [ON Semiconductor]
Direct Link  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

MC74LVX259DR2G Datasheet(HTML) 5 Page - ON Semiconductor

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MC74LVX259
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5
DC CHARACTERISTICS (Voltages Referenced to GND)
VCC
TA = 25°C
−40
°C ≤ TA ≤ 85°C
Symbol
Parameter
Condition
(V)
Min
Typ
Max
Min
Max
Unit
VIH
Minimum High−Level
Input Voltage
2.0
3.0
3.6
0.75 VCC
0.7 VCC
0.7 VCC
0.75 VCC
0.7 VCC
0.7 VCC
V
VIL
Maximum Low−Level
Input Voltage
2.0
3.0
3.6
0.25 VCC
0.3 VCC
0.3 VCC
0.25 VCC
0.3 VCC
0.3 VCC
V
VOH
High−Level Output
Voltage
IOH = −50 mA
2.0
1.9
2.0
1.9
V
Voltage
IOH = −50 mA
3.0
2.9
3.0
2.9
IOH = −4 mA
3.0
2.58
2.48
VOL
Low−Level Output
Voltage
IOL = 50 mA
2.0
0.0
0.1
0.1
V
Voltage
IOL = 50 mA
3.0
0.0
0.1
0.1
IOL = 4 mA
3.0
0.36
0.44
IIN
Input Leakage Current
VIN = 5.5 V or GND
0 to 3.6
±0.1
±1.0
mA
ICC
Maximum Quiescent
Supply Current
(per package)
VIN = VCC or GND
3.6
1.0
1.0
2.0
mA
AC ELECTRICAL CHARACTERISTICS Input tr = tf = 3.0 ns
TA = 25°C
−40
°C ≤ TA ≤ 85°C
Symbol
Parameter
Test Conditions
Min
Typ
Max
Min
Max
Unit
tPLH,
tPHL
Maximum Propagation
Delay, Data to Output
(Figures 5 and 9)
VCC = 2.7 V
CL = 15pF
CL = 50pF
6.3
9.0
9.0
14.0
1.0
1.0
12.0
15.0
ns
(Figures 5 and 9)
VCC = 3.3 V ± 0.3 V
CL = 15pF
CL = 50pF
5.6
8.0
8.0
12.0
1.0
1.0
11.0
14.0
tPLH,
tPHL
Maximum Propagation
Delay, Address Select
to Output
VCC = 2.7 V
CL = 15pF
CL = 50pF
6.3
9.0
9.0
14.0
1.0
1.0
12.0
15.0
ns
to Output
(Figures 6 and 9)
VCC = 3.3 V ± 0.3 V
CL = 15pF
CL = 50pF
5.6
8.0
8.0
12.0
1.0
1.0
11.0
14.0
tPLH,
tPHL
Maximum Propagation
Delay, Enable to Output
(Figures 7 and 9)
VCC = 2.7 V
CL = 15pF
CL = 50pF
6.3
9.0
9.0
14.0
1.0
1.0
12.0
15.0
ns
(Figures 7 and 9)
VCC = 3.3 V ± 0.3 V
CL = 15pF
CL = 50pF
5.6
8.0
9.0
12.0
1.0
1.0
11.0
14.0
tPHL
Maximum Propogation
Delay, Reset to Output
(Figures 7 and 9)
VCC = 2.7 V
CL = 15pF
CL = 50pF
6.3
9.0
9.0
14.0
1.0
1.0
12.0
15.0
ns
(Figures 7 and 9)
VCC = 3.3 V ± 0.3 V
CL = 15pF
CL = 50pF
5.6
8.0
9.0
12.0
1.0
1.0
11.0
14.0
CIN
Maximum Input
Capacitance
6
10
10
pF
Typical @ 25
°C, VCC = 3.3 V
CPD
Power Dissipation Capacitance (Note 5)
30
pF
5. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: ICC(OPR) = CPD  VCC  fin + ICC. CPD is used to determine the no−load dynamic
power consumption; PD = CPD  VCC2  fin + ICC  VCC.


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