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Loopback Testing

ENABLE Function

PRBS Function

TLK1221

SLLS713 – FEBRUARY 2007

The transceiver can provide a self-test function by enabling (LOOPEN to high level) the internal loopback path.

Enabling this function causes serial transmitted data to be routed internally to the receiver. The parallel data

output can be compared to the parallel input data for functional verification. (The external differential output is

held in a high-impedance state during the loopback testing.)

When held low, ENABLE disables all quiescent power in both analog and digital circuitry. This allows an

ultralow-power idle state when the link is not active.

enabled. A PRBS is generated and fed into the 10-bit parallel transmitter input bus. Data from the normal

parallel input source is ignored during PRBS test mode. The PRBS pattern is then fed through the transmit

circuitry as if it were normal data and sent out to the transmitter. The output can be sent to a bit error rate tester

(BERT) or to the receiver of another TLK1221. Because the PRBS is not really random and is really a

predetermined sequence of ones and zeros, the data can be captured and checked for errors by a BERT. These

devices also have a built-in BERT function on the receiver side that is enabled by PRBSEN. It can receive a

PRBS pattern and check for errors, and then report the errors by forcing the SYNC/PASS terminal low. The

PRBS testing supports two modes (normal and latched), which are controlled by the SYNCEN input. When

SYNCEN is low, the result of the PRBS bit-error-rate test is passed to the SYNC/PASS terminal. When

SYNCEN is high, the result of the PRBS verification is latched on the SYNC/PASS output (i.e., a single failure

forces SYNC/PASS to remain low).

Table 2. TERMINAL FUNCTIONS

TERMINAL

I/O

DESCRIPTION

NAME

NO.

SIGNAL

Differential output transmit. TXP and TXN are differential serial outputs that interface to a

TXP

38

PECL

copper or an optical I/F module. TXP and TXN are put in a high-impedance state when

TXN

39

O

LOOPEN is high and are active when LOOPEN is low.

RXP

34

PECL

Differential input receive. RXP and RXN together are the differential serial input interface

RXN

33

I

from a copper or an optical I/F module.

Reference clock. REFCLK is an external input clock that synchronizes the receiver and

transmitter interface (60 MHz to 130 MHz). The transmitter uses this clock to register the

REFCLK

14

I

input data (TD0–TD9) for serialization.

In the TBI mode that data is registered on the rising edge of REFCLK.

Transmit data. These inputs carry 10-bit parallel data output from a protocol device to the

transceiver for serialization and transmission. This 10-bit parallel data is clocked into the

TD0–TD9

2–5, 7–12

I

transceiver on the rising edge of REFCLK and transmitted as a serial stream with TD0 sent

as the first bit.

Receive data. These outputs carry 10-bit parallel data output from the transceiver to the

RD0–RD9

29–27, 25–19

O

protocol layer. The data is referenced to terminals RBC0 and RBC1. RD0 is the first bit

received.

Receive byte clock. RBC0 and RBC1 are recovered clocks used for synchronizing the 10-bit

output data on RD0–RD9.

In the half-rate mode, the 10-bit output data words are valid on the rising edges of RBC0

RBC0

17

and RBC1. These clocks are adjusted to half-word boundaries in conjunction with

O

RBC1

18

synchronous detect. The clocks are always expanded during data realignment and never

slivered or truncated. RBC0 registers bytes 1 and 3 of received data. RBC1 registers bytes 0

and 2 of received data. In normal-rate mode, only RBC0 is valid and operates at 1/10th the

serial data rate. Data is aligned to the rising edge.

Receive clock mode select. When RBCMODE is low, half-rate clocks are output on RBC0

I

RBCMODE

13

and RBC1. When RBCMODE is high, a full baud-rate clock is output on RBC0, and RBC1 is

held low.

(1)

P/D = Internal pulldown resistor

6

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