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ADSP-21369KBP-2A Datasheet(PDF) 5 Page - Analog Devices |
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ADSP-21369KBP-2A Datasheet(HTML) 5 Page - Analog Devices |
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5 / 56 page  ADSP-21367/ADSP-21368/ADSP-21369 Rev. A | Page 5 of 56 | August 2006 ALU and multiplier operations occur in both processing ele- ments. These computation units support IEEE 32-bit single- precision floating-point, 40-bit extended precision floating- point, and 32-bit fixed-point data formats. Data Register File A general-purpose data register file is contained in each pro- cessing element. The register files transfer data between the computation units and the data buses, and store intermediate results. These 10-port, 32-register (16 primary, 16 secondary) register files, combined with the ADSP-2136x enhanced Har- vard architecture, allow unconstrained data flow between computation units and internal memory. The registers in PEX are referred to as R0–R15 and in PEY as S0–S15. Single-Cycle Fetch of Instruction and Four Operands The ADSP-21367/ADSP-21368/ADSP-21369 feature an enhanced Harvard architecture in which the data memory (DM) bus transfers data and the program memory (PM) bus transfers both instructions and data (see Figure 1 on Page 1). With separate program and data memory buses and on-chip instruction cache, the processors can simultaneously fetch four operands (two over each data bus) and one instruction (from the cache), all in a single cycle. Instruction Cache The processors include an on-chip instruction cache that enables three-bus operation for fetching an instruction and four data values. The cache is selective—only the instructions whose fetches conflict with PM bus data accesses are cached. This cache allows full-speed execution of core, looped operations such as digital filter multiply-accumulates, and FFT butterfly processing. Data Address Generators with Zero-Overhead Hardware Circular Buffer Support The ADSP-21367/ADSP-21368/ADSP-21369 have two data address generators (DAGs). The DAGs are used for indirect addressing and implementing circular data buffers in hardware. Circular buffers allow efficient programming of delay lines and other data structures required in digital signal processing, and are commonly used in digital filters and Fourier transforms. The two DAGs contain sufficient registers to allow the creation of up to 32 circular buffers (16 primary register sets, 16 second- ary). The DAGs automatically handle address pointer wraparound, reduce overhead, increase performance, and sim- plify implementation. Circular buffers can start and end at any memory location. Flexible Instruction Set The 48-bit instruction word accommodates a variety of parallel operations, for concise programming. For example, the ADSP-21367/ADSP-21368/ADSP-21369 can conditionally exe- cute a multiply, an add, and a subtract in both processing elements while branching and fetching up to four 32-bit values from memory—all in a single instruction. MEMORY ARCHITECTURE The ADSP-21367/ADSP-21368/ADSP-21369 processors add the following architectural features to the SIMD SHARC family core. On-Chip Memory The processors contain two megabits of internal RAM and six megabits of internal mask-programmable ROM. Each block can be configured for different combinations of code and data stor- age (see Table 2 on Page 6). Each memory block supports single-cycle, independent accesses by the core processor and I/O processor. The memory architecture, in combination with its separate on-chip buses, allow two data transfers from the core and one from the I/O processor, in a single cycle. The SRAM can be configured as a maximum of 64K words of 32-bit data, 128K words of 16-bit data, 42K words of 48-bit instructions (or 40-bit data), or combinations of different word sizes up to two megabits. All of the memory can be accessed as 16-bit, 32-bit, 48-bit, or 64-bit words. A 16-bit floating-point storage format is supported that effectively doubles the amount of data that may be stored on-chip. Conversion between the 32-bit floating-point and 16-bit floating-point formats is per- formed in a single instruction. While each memory block can store combinations of code and data, accesses are most efficient when one block stores data using the DM bus for transfers, and the other block stores instructions and data using the PM bus for transfers. Using the DM bus and PM buses, with one bus dedicated to each memory block, assures single-cycle execution with two data transfers. In this case, the instruction must be available in the cache. EXTERNAL MEMORY The external port provides a high performance, glueless inter- face to a wide variety of industry-standard memory devices. The 32-bit wide bus may be used to interface to synchronous and/or asynchronous memory devices through the use of its separate internal memory controllers. The first is an SDRAM controller for connection of industry-standard synchronous DRAM devices and DIMMs (Dual Inline Memory Module), while the second is an asynchronous memory controller intended to interface to a variety of memory devices. Four memory select pins enable up to four separate devices to coexist, supporting any desired combination of synchronous and asynchronous device types. NonSDRAM external memory address space is shown in Table 3. SDRAM Controller The SDRAM controller provides an interface of up to four sepa- rate banks of industry-standard SDRAM devices or DIMMs, at speeds up to fSCLK. Fully compliant with the SDRAM standard, each bank has its own memory select line (MS0–MS3), and can be configured to contain between 16M bytes and 128M bytes of memory. SDRAM external memory address space is shown in Table 4. |
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