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A3950SEUTR-T Datasheet(PDF) 7 Page - Allegro MicroSystems |
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A3950SEUTR-T Datasheet(HTML) 7 Page - Allegro MicroSystems |
7 / 12 page DMOS Full-Bridge Motor Driver A3950 7 Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com Device Operation . The 3950 is designed to operate one dc motor. The currents in the output full-bridges, all N-channel DMOS, are regulated with fixed off-time pulse width modulated (PWM) control circuitry. Logic Inputs. If logic inputs are pulled up to VDD, it is good practice to use a high value pull-up resistor in order to limit cur- rent to the logic inputs should an overvoltage event occur. Logic inputs include: SLEEP, MODE, PHASE, and ENABLE. The voltage on any logic input cannot exceed the specified maximum of 7 V. VREG . This supply voltage is used to run the sink-side DMOS outputs. VREG is internally monitored and in the case of a fault condition, the outputs of the device are disabled. The VREG pin should be decoupled with a 0.22 μF capacitor to ground. Charge Pump . The charge pump is used to generate a sup- ply above VBB to drive the source-side DMOS gates. A 0.1 μF ceramic monolithic capacitor should be connected between CP1 and CP2 for pumping purposes. A 0.1 μF ceramic monolithic capacitor should be connected between VCP and VBB to act as a reservoir to run the high-side DMOS devices. The VCP voltage level is internally monitored and, in the case of a fault condition, the outputs of the device are disabled. Shutdown . In the event of a fault due to excessive junction temperature, or low voltage on VCP or VREG, the outputs of the device are disabled until the fault condition is removed. At power-on the UVLO circuit disables the drivers. Sleep Mode . Control input SLEEP is used to minimize power consumption when the A3950 is not in use. This disables much of the internal circuitry, including the regulator and charge pump. A logic low setting puts the device into Sleep mode, and a logic high setting allows normal operation. After coming out of Sleep mode, provide a 1 ms interval before applying PWM signals, to allow the charge pump to stabilize. MODE . Control input MODE is used to toggle between fast decay mode and slow decay mode. A logic high puts the device in slow decay mode. Synchronous rectification is always enabled. Braking . The braking function is implemented by driving the device in slow decay mode via the MODE setting and applying an enable chop command. Because it is possible to drive current in both directions through the DMOS switches, this configuration effectively shorts out the motor generated BEMF as long as the ENABLE chop mode is asserted. The maximum current can be approximated by VBEMF/RL. Care should be taken to insure that the maximum ratings of the device are not exceeded in worse case braking situations: high speed and high-inertia loads. Diagnostic Output . The NFAULT pin signals a problem with the chip via an open drain output. A motor fault, undervoltage condition, or TJ > 160°C will drive the pin active low. This output is not valid when SLEEP puts the device into minimum power dissipation mode. TSD . Two die temperature monitors are integrated on the chip. As die temperature increases towards the maximum, a thermal warning signal will be triggered at 160°C. This fault drives the NFAULT low, but does not disable the operation of the chip. If the die temperature increases further, to approximately 175°C, the full-bridge outputs will be disabled until the internal temperature falls below a hysteresis of 15°C. Functional Description Control Logic Table1 Pin Function PHASE ENABLE MODE SLEEP OUTA OUTB 1 1 X 1 H L Forward 0 1 X 1 L H Reverse X 0 1 1 L L Brake (slow decay) 1001 L H Fast Decay Synchronous Rectification2 0001 H L Fast Decay Synchronous Rectification2 X X X 0 Z Z Sleep Mode 1X indicates “don’t care,” Z indicates high impedance. 2 To prevent reversal of current during fast decay synchronous rectification, outputs go to the high impedance state as the current approaches 0 A. |
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