MC74HC4040A

http://onsemi.com

5

Symbol

Parameter

V

Guaranteed Limit

Unit

−55 to 25

°C

≤85°C

≤125°C

Minimum Recovery Time, Reset Inactive to Clock

(Figure 2)

2.0

3.0

4.5

6.0

30

20

5

4

40

25

8

6

50

30

12

9

ns

Minimum Pulse Width, Clock

(Figure 1)

2.0

3.0

4.5

6.0

70

40

15

13

80

45

19

16

90

50

24

20

ns

Minimum Pulse Width, Reset

(Figure 2)

2.0

3.0

4.5

6.0

70

40

15

13

80

45

19

16

90

50

24

20

ns

Maximum Input Rise and Fall Times

(Figure 1)

2.0

3.0

4.5

6.0

1000

800

500

400

1000

800

500

400

1000

800

500

400

ns

NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book

(DL129/D).

PIN DESCRIPTIONS

INPUTS

Clock (Pin 10)

Negative−edge triggering clock input. A high−to−low

transition on this input advances the state of the counter.

Reset (Pin 11)

Active−high reset. A high level applied to this input

asynchronously resets the counter to its zero state, thus

forcing all Q outputs low.

OUTPUTS

Q1 thru Q12 (Pins 9, 7, 6, 5, 3, 2, 4, 13, 12, 14, 15, 1)

Active−high outputs. Each Qn output divides the Clock

SWITCHING WAVEFORMS

Clock

Q1

GND

90%

50%

10%

90%

50%

10%

Clock

GND

50%

Figure 3.

Reset

GND

50%

Any Q

50%

Figure 4.