MC74HCT574A

http://onsemi.com

4

Symbol

Parameter

Guaranteed Limit

Unit

– 55 to

25

_C

v 85_C

v 125_C

Maximum Clock Frequency (50% Duty Cycle) (Figures 3 and 6)

30

24

20

MHz

Maximum Propagation Delay, Clock to Q

(Figures 3 and 6)

30

38

45

ns

Maximum Propagation Delay, Output Enable to Q

(Figures 4 and 7)

28

35

42

ns

Maximum Propagation Delay Time, Output Enable to Q

(Figures 4 and 7)

28

35

42

ns

Maximum Output Transition Time, Any Output

(Figures 3, 4 and 6)

12

15

18

ns

Maximum Input Capacitance

10

10

10

pF

NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON

Semiconductor High−Speed CMOS Data Book (DL129/D).

Power Dissipation Capacitance (Per Flip−Flop)*

Typical @ 25

pF

58

ON Semiconductor High−Speed CMOS Data Book (DL129/D).

Symbol

Parameter

Figure

Guaranteed Limit

Unit

– 55 to 25

_C

v 85_C

v 125_C

Min

Max

Min

Max

Min

Max

Minimum Setup Time, Data to Clock

5

10

13

15

ns

Minimum Hold Time, Clock to Data

5

5.0

5.0

5.0

ns

Minimum Pulse Width, Clock

3

15

19

22

ns

Maximum Input Rise and Fall Times

3

500

500

500

ns

EXPANDED LOGIC DIAGRAM

CLOCK

ENABLE

OUTPUT

11

1

D0

2

C

19

D

Q

Q0

D1

3

C

18

D

Q

Q1

D2

4

C

17

D

Q

Q2

D3

5

C

16

D

Q

Q3

D4

6

C

15

D

Q

Q4

D5

7

C

14

D

Q

Q5

D6

8

C

13

D

Q

Q6

D7

9

C

12

D

Q

Q7