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MC74HC540ANG Datasheet(PDF) 4 Page - ON Semiconductor |
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MC74HC540ANG Datasheet(HTML) 4 Page - ON Semiconductor |
4 / 8 page MC74HC540A http://onsemi.com 4 DC CHARACTERISTICS (Voltages Referenced to GND) VCC V Guaranteed Limit Symbol Parameter Condition −55 to 25 °C ≤85°C ≤125°C Unit VIH Minimum High−Level Input Voltage Vout = 0.1 V |Iout| ≤ 20 mA 2.0 3.0 4.5 6.0 1.50 2.10 3.15 4.20 1.50 2.10 3.15 4.20 1.50 2.10 3.15 4.20 V VIL Maximum Low−Level Input Voltage Vout = VCC − 0.1 V |Iout| ≤ 20 mA 2.0 3.0 4.5 6.0 0.50 0.90 1.35 1.80 0.50 0.90 1.35 1.80 0.50 0.90 1.35 1.80 V VOH Minimum High−Level Output Voltage Vin = VIL |Iout| ≤ 20 mA 2.0 4.5 6.0 1.9 4.4 5.9 1.9 4.4 5.9 1.9 4.4 5.9 V Vin = VIL |Iout| ≤ 3.6 mA |Iout| ≤ 6.0 mA |Iout| ≤ 7.8 mA 3.0 4.5 6.0 2.48 3.98 5.48 2.34 3.84 5.34 2.20 3.70 5.20 VOL Maximum Low−Level Output Voltage Vin = VIH |Iout| ≤ 20 mA 2.0 4.5 6.0 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 V Vin = VIH |Iout| ≤ 3.6 mA |Iout| ≤ 6.0 mA |Iout| ≤ 7.8 mA 3.0 4.5 6.0 0.26 0.26 0.26 0.33 0.33 0.33 0.40 0.40 0.40 Iin Maximum Input Leakage Current Vin = VCC or GND 6.0 ±0.1 ±1.0 ±1.0 mA IOZ Maximum Three−State Leakage Current Output in High Impedance State Vin = VIL or VIH Vout = VCC or GND 6.0 ±0.5 ±5.0 ±10.0 mA ICC Maximum Quiescent Supply Current (per Package) Vin = VCC or GND Iout = 0 mA 6.0 4 40 160 mA 7. Information on typical parametric values can be found in the ON Semiconductor High−Speed CMOS Data Book (DL129/D). AC CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns) VCC V Guaranteed Limit Symbol Parameter −55 to 25 °C ≤85°C ≤125°C Unit tPLH, tPHL Maximum Propagation Delay, Input A to Output Y (Figures 3 and 5) 2.0 3.0 4.5 6.0 80 30 18 15 100 40 23 20 120 55 28 25 ns tPLZ, tPHZ Maximum Propagation Delay, Output Enable to Output Y (Figures 4 and 6) 2.0 3.0 4.5 6.0 110 45 25 21 140 60 31 26 165 75 38 31 ns tPZL, tPZH Maximum Propagation Delay, Output Enable to Output Y (Figures 4 and 6) 2.0 3.0 4.5 6.0 110 45 25 21 140 60 31 26 165 75 38 31 ns tTLH, tTHL Maximum Output Transition Time, Any Output (Figures 3 and 5) 2.0 3.0 4.5 6.0 60 22 12 10 75 28 15 13 90 34 18 15 ns Cin Maximum Input Capacitance 10 10 10 pF Cout Maximum 3−State Output Capacitance (Output in High Impedance State) 15 15 15 pF 8. For propagation delays with loads other than 50 pF, and information on typical parametric values, see the ON Semiconductor High−Speed CMOS Data Book (DL129/D). CPD Power Dissipation Capacitance (Per Buffer) (Note 9) Typical @ 25 °C, VCC = 5.0 V, VEE = 0 V pF 35 9. Used to determine the no−load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see the ON Semiconductor High−Speed CMOS Data Book (DL129/D). |
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