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MC74HC161ADR2G Datasheet(PDF) 6 Page - ON Semiconductor |
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MC74HC161ADR2G Datasheet(HTML) 6 Page - ON Semiconductor |
6 / 16 page MC74HC161A, MC74HC163A http://onsemi.com 6 TIMING REQUIREMENTS (CL = 50 pF, Input tr = tf = 6.0 ns) Symbol Parameter Figure VCC V Guaranteed Limit Unit – 55 to 25_C v 85_C v 125_C tsu Minimum Setup Time, Preset Data Inputs to Clock 8 2.0 3.0 4.5 6.0 40 20 15 12 60 30 20 18 80 40 30 20 ns tsu Minimum Setup Time, Load to Clock 8 2.0 3.0 4.5 6.0 60 25 15 12 75 30 20 18 90 40 30 20 ns tsu Minimum Setup Time, Reset to Clock (HC163A Only) 7 2.0 3.0 4.5 6.0 60 25 20 17 75 30 25 23 90 40 35 25 ns tsu Minimum Setup Time, Enable T or Enable P to Clock 9 2.0 3.0 4.5 6.0 80 35 20 17 95 40 25 23 110 50 35 25 ns th Minimum Hold Time, Clock to Load or Preset Data Inputs 8 2.0 3.0 4.5 6.0 3 3 3 3 3 3 3 3 3 3 3 3 ns th Minimum Hold Time, Clock to Reset (HC163A Only) 7 2.0 3.0 4.5 6.0 3 3 3 3 3 3 3 3 3 3 3 3 ns th Minimum Hold Time, Clock to Enable T or Enable P 9 2.0 3.0 4.5 6.0 3 3 3 3 3 3 3 3 3 3 3 3 ns trec Minimum Recovery Time, Reset Inactive to Clock (HC161A Only) 5 2.0 3.0 4.5 6.0 80 35 15 12 95 40 20 17 110 50 26 23 ns trec Minimum Recovery Time, Load Inactive to Clock 8 2.0 3.0 4.5 6.0 80 35 15 12 95 40 20 17 110 50 26 23 ns tw Minimum Pulse Width, Clock 4 2.0 3.0 4.5 6.0 60 25 12 10 75 30 15 13 90 40 18 15 ns tw Minimum Pulse Width, Reset (HC161A Only) 5 2.0 3.0 4.5 6.0 60 25 12 10 75 30 15 13 90 40 18 15 ns tr, tf Maximum Input Rise and Fall Times 2.0 3.0 4.5 6.0 1000 800 500 400 1000 800 500 400 1000 800 500 400 ns |
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