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SP8782MP Datasheet(PDF) 3 Page - Zarlink Semiconductor Inc |
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SP8782MP Datasheet(HTML) 3 Page - Zarlink Semiconductor Inc |
3 / 8 page 3 SP8782A & B DON’T CARE 8 (16) tr tr 8 (16) 9 (17) CLOCK INPUT MODULUS CONTROL INPUT OUTPUT DON’T CARE 8 (16) DIVIDE-BY-17 (33) MODE ESTABLISHED EXTRA PULSE Fig. 3a Setting divide-by-16 (32) mode DON’T CARE 9 (17) ts ts 8 (16) 8 (16) CLOCK INPUT MODULUS CONTROL INPUT OUTPUT DON’T CARE 8 (16) DIVIDE-BY-16 (32) MODE ESTABLISHED Figure 3 Timing diagrams Table 1 Truth table for control inputs Modulus control Ratio select input input 01 0 ÷17 ÷33 1 ÷16 ÷32 Figure 3b Setting divide - by - 17 (33 mode) Figure 3a Setting divide - by - 16 (32 mode) |
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