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PDSP16510AMA Datasheet(PDF) 10 Page - Zarlink Semiconductor Inc |
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PDSP16510AMA Datasheet(HTML) 10 Page - Zarlink Semiconductor Inc |
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10 / 23 page  PDSP16510A 10 data and scale tag outputs will go high impedance after the delay shown in Table 3. Valid transformed data is actually available within the device from DAV going active until INEN again goes active, and a new set of data is loaded. The output tristate drivers, however, normally go high impedance when DAV goes in- active once a dump operation has been completed. In order to support systems in which it may be necessary to read the transformed data more than once, a Control Register Bit is provided which keeps the DAV output active until a further INEN edge is received. The user must then keep track of how many outputs have been dumped before INEN is generated to start a new load operation. The DAV output can be delayed by an amount equivalent to the pipeline delay through the PDSP16330. This option is invoked by setting a control bit, and allows DAV to indicate that polar data is available at the output of the PDSP16330. When the option is used the tri-state outputs will be enabled when data is actually available and DEN is active, and not when DAV eventually goes active. Two Control Register Bits allow a range of dump size options to be supported. In some applications the results of interest may only lie in the lower 25 or 50% of the frequency bins, the sampling rate having been chosen to prevent aliasing, and the transform size having been selected to give the required frequency resolution. In other systems it is only necessary to output the second half of a given sized transform. This is useful when filtering is to be performed in the frequency domain using Overlap /Discard Fast Convolutions. With this method FIR filters with N taps can be implemented in the frequency domain using 50% overlapped transforms on 2N samples. After multiplication in the frequency domain with the required frequency response, the inverse transform is per- formed and the first half of each output is discarded. Since only half the results are dumped, the dump clock need not be twice the rate of the clock used to load data. FULL CO - PROCESSOR OPERATION A single device can be configured as a co-processor to a host system in which both the loading and dumping of data is under the control of the host. Such a system is shown in Figure 7, in which DEN is a host provided enable for host read operations, and INEN is an enable for host write operations. DIS and DOS are host data strobes. The host loads a block of data into the PDSP16510, using DIS enabled by INEN, which is then automatically trans- formed. The DAV output provides a flag indicating that the transform is complete, and results are then read by the host using DOS enabled by DEN. A new set of inputs is not normally loaded until the previous results are complete. If, however, 1024 point transforms are not to be performed, loading new data could coincide with dumping previous re- sults. This, however, would require a host system with sepa- rate input and output buses, and which also allowed coinci- dent transfers. As discussed previously, transferring results must take no longer than loading new data to prevent corrup- tion of the outputs. In the system illustrated by Figure 7, the host also controls the mode of operation of the FFT processor. The DEF signal is produced from an address decode, and the control parame- ters are loaded from the host bus by connecting the AUX inputs to the data outputs. REAL ONLY TRANSFORMS WITH A SINGLE DEVICE In the simplest case real transforms can, of course, be computed by forcing zero levels on the imaginary input pins. The device can, however, be configured to internally perform two simultaneous real transforms instead of a single complex transform. The block floating point logic will then use data from both blocks when it determines the number of shifts to be applied. This dual transform technique is used to increase the maximum permissible sampling rates, but since an additional data pass is required in order to un-scramble the transformed data, the actual performance is not quite double that possible with a complex transform of the same size. The 4 x 64 point complex mode becomes an 8 x 64 real mode, but the change from 16 x 16 complex transforms to 32 x 16 real transforms is not supported. When a real transform is performed the algorithm pro- duces complex results for each of the incoming data blocks, but each result only represents the first half of the frequency domain data. This does not cause any loss of information since the two halves are mirror images of each other. As with complex transforms, it is necessary for a different system configuration to be used when 1024 point transforms are required. These are considered later, and the following only applies to 256 or 64 point transforms. D I R PDSP16510 AUX POWER ON RESET PARAMETERS PDSP 16540 BUCKET BUFFER GND WS RS DAV REAL ONLY SAMPLE CLOCK SYSTEM CLOCK MD5 +5V MD4:0 GND RES DIN O/P S3:0 PDSP16510 AUX SYSTEM CLOCK HOST SYSTEM Fig. 7. Host Controlled System Fig 8. 1024 Point Real Transforms |
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