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PDSP16330MC Datasheet(PDF) 3 Page - Zarlink Semiconductor Inc

Part # PDSP16330MC
Description  Pythagoras Processor
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Manufacturer  ZARLINK [Zarlink Semiconductor Inc]
Direct Link  http://www.zarlink.com
Logo ZARLINK - Zarlink Semiconductor Inc

PDSP16330MC Datasheet(HTML) 3 Page - Zarlink Semiconductor Inc

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PDSP16330 MC
3
PIN DESCRIPTIONS
Symbol
Pin Name and Description
CLK
Clock: Common Clock to device Registers. Register contents change on the rising edge of clock.
Both pins must be connected.
CEX
Clock Enable: Clock Enable for X Port. The clock to the X port is enabled by a low level.
CEY
Clock Enable: Clock Enable for Y Port The clock to the Y port is enabled by a low level.
X15-X0
X Data Input Data presented to this input is loaded into the device by the rising edge of CLK.
X15 is the MSB
Y15-Y0
Y Data Input Data presented to this input is loaded into the device by the rising edge of CLK.
Y15 is the MSB
M15-M0
M Data Output: Magnitude data generated by the device is output on this port. Data changes on
the rising edge of CLK, M15 is the MSB. The weighting of M15 is determined by the Scale factor
selected .
P11-P0
P Data Output: Phase data generated by the device is output on this port. Data changes on the
rising edge of CLK, P11 is the MSB. The weighting of P11 is
π radians.
OEM
Output Enable: Output Enable for M Port. The M Port is in a high impedance state when this input
is high.
OEP
Output Enable: Output Enable for P Port. The P Port is in a high impedance state when this input
is high.
FORM
Format Select This input selects the format of the Cartesian Data input on the X and Y ports.
This input is latched by the rising edge of CLK, and is applied at the same time as the data to
which it refers. A low !evel indicates that two’s complement data is applied, a high indicates
Sign-Magnitude
S1-S0
Scaling Control: Control input for scaling of Magnitude Data. This input is latched by the rising
edge of CLK, and determines the scaling to be applied to the Magnitude result. The Scaling is
applied to the output data in the cycle following the cycle in which the control was latched.
OVR
Overflow: Overflow flag. This signal becomes active if the scaling currently selected causes an
invalid value to be presented to the Magnitude output.
Vcc
+5V supply. All Vcc pins must be connected.
GND
0V supply. All GND pins must be connected.
2's Complement
7FFF
.
.
.
0001
0000
FFFF
.
.
.
8001
Sign Magnitude
7FFF
.
.
.
0001
.
.
.
FFF
0000
8000
INPUT DATA RANGE


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