PDSP16116/A/MC

9

ii) WTB1:0 = 00 No shift applied giving a shifter output format:

iii) WTB1:0 = 01 Shift complex product one place to the right

giving a shifter output format:

iv) WTB1:0 = 10 Shift complex product two places to the right

giving a shifter output format:

Overflow

If the left shift option is selected and the Adder/Subtractor

contain a 32 bit word, then an invalid result will be passed to

the output. An invalid output arising from this combination of

events will be flagged by the SFTA0 flag output. The SFTA0

Flag will go high if either the real or imaginary reslut is invalid.

Output Select

The output from the Shifters is passed to the Output Select

Mux, which is controlled via the OSEL inputs. These inputs

are not registered and hence allow the output combination to

be changed within each cycle. The full complex 64 bit result

from the multiplier may therefore be output within a single

cycle.

The OSEL control selects four different output

combinations as as summarised in Table 4.

PR

MSR

LSR

MSR

MSI

PI

MSI

LSI

LSR

LSI

OSEL0

0

1

0

1

OSEL1

0

0

1

1

Table 3 - Output Selection

(Where MSR and LSR are the most and least siginificant 16 bit

words of the Real Shifter output, MSI and LSI are the most and

least significant 16 bit words of the imaginary Shifter output).

The output select options allow two different modes for

extracting the full 32 bit result from the PDSP16116. The first

mode treats the two 16 bit outputs as real and imaginary ports

allowing the real and imaginary results to be output in two

halves on the real and imaginary output ports. The second

mode treats the two 16 bit outputs as one 32 bit output and

allows the real and imaginary results to be output as 32 bit

words.

PIN DESCRIPTIONS

XR, XI, YR, YI

Data inputs 16 bits: Data is loaded into the input registers

from these ports on the rising edge of CLK. The data format

is Twos Complement Fractional, where the MSB (sign bit) is

bit 15. In normal mode the weighting of the MSB is -20 ie -1.

PR, PI

Data outputs 16 bits: Data is clocked into the output

registers and passed to the PR and PI outputs on the rising

edge of CLK.

The data format is Twos Complement

Fractional. The field of the internal result selected for output

via PR and PI is controlled by signals OSEL1:0 (see Table 4).

CLK

Common Clock to all internal register.

CEX, CEY

Clock enables for X and Y input ports: When low these

inputs enable the CLK signal to the X or Y input registers

allowing new data to be clocked into the Multiplier.

CONX, CONY

If either of these inputs are high on the rising edge of CLK,

then the data in the associated input has its imaginary

component inverted (multiplied by -1), see Table 3. CONX

and CONY affect data input on the same clock rising edge.

ROUND

The ROUND control is used to round the most siginficant

16 bits of the Adder/Subtractor result prior to being passed to

the output register. The rounding operation takes place one

cycle after the ROUND input is taken high. The ROUND input

is not latched and is intended to be tied high or low depending

upon the application.

MBFP

Mode select: When high, Block Floating Point (BFP) mode

is selected. This allows the device to maintain the dynamic

range of the data using a series of word tags. This is especially

useful in FFT appllications. When low, the chip operates in

normal mode for more general applications.

This pin is

intended to be tied high or low, depending on application.

Bit Number

30

Weighting

29 28 27 26

6543210

S

2

2

2

2

2

2

2

2

2

2

0

31

2

2

2

1

25

2

24

Bit Number

30

Weighting

29 28 27 26

76543210

S

2

2

2

2

2

2

2

2

2

2

2

0

31

2

8

2

Bit Number

30

Weighting

29 28 27 26

6543210

S

2

2

2

2

2

2

2

2

2

0

31

2

2

2

1

25 24

2

2

2