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MC74HC4053ADR2G Datasheet(PDF) 5 Page - ON Semiconductor |
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MC74HC4053ADR2G Datasheet(HTML) 5 Page - ON Semiconductor |
5 / 18 page MC74HC4051A, MC74HC4052A, MC74HC4053A http://onsemi.com 5 DC CHARACTERISTICS — Analog Section Symbol Parameter Condition VCC VEE Guaranteed Limit Unit −55 to 25 °C ≤85°C ≤125°C Ron Maximum “ON” Resistance Vin = VIL or VIH; VIS = VCC to VEE; IS ≤ 2.0 mA (Figures 1, 2) 4.5 4.5 6.0 0.0 − 4.5 − 6.0 190 120 100 240 150 125 280 170 140 W Vin = VIL or VIH; VIS = VCC or VEE (Endpoints); IS ≤ 2.0 mA (Figures 1, 2) 4.5 4.5 6.0 0.0 − 4.5 − 6.0 150 100 80 190 125 100 230 140 115 DRon Maximum Difference in “ON” Resistance Between Any Two Channels in the Same Package Vin = VIL or VIH; VIS = 1/2 (VCC − VEE); IS ≤ 2.0 mA 4.5 4.5 6.0 0.0 − 4.5 − 6.0 30 12 10 35 15 12 40 18 14 W Ioff Maximum Off−Channel Leakage Current, Any One Channel Vin = VIL or VIH; VIO = VCC − VEE; Switch Off (Figure 3) 6.0 − 6.0 0.1 0.5 1.0 mA Maximum Off−ChannelHC4051A Leakage Current, HC4052A Common Channel HC4053A Vin = VIL or VIH; VIO = VCC − VEE; Switch Off (Figure 4) 6.0 6.0 6.0 − 6.0 − 6.0 − 6.0 0.2 0.1 0.1 2.0 1.0 1.0 4.0 2.0 2.0 Ion Maximum On−ChannelHC4051A Leakage Current, HC4052A Channel−to−Channel HC4053A Vin = VIL or VIH; Switch−to−Switch = VCC − VEE; (Figure 5) 6.0 6.0 6.0 − 6.0 − 6.0 − 6.0 0.2 0.1 0.1 2.0 1.0 1.0 4.0 2.0 2.0 mA AC CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns) Symbol Parameter VCC V Guaranteed Limit Unit −55 to 25 °C ≤85°C ≤125°C tPLH, tPHL Maximum Propagation Delay, Channel−Select to Analog Output (Figure 9) 2.0 3.0 4.5 6.0 270 90 59 45 320 110 79 65 350 125 85 75 ns tPLH, tPHL Maximum Propagation Delay, Analog Input to Analog Output (Figure 10) 2.0 3.0 4.5 6.0 40 25 12 10 60 30 15 13 70 32 18 15 ns tPLZ, tPHZ Maximum Propagation Delay, Enable to Analog Output (Figure 11) 2.0 3.0 4.5 6.0 160 70 48 39 200 95 63 55 220 110 76 63 ns tPZL, tPZH Maximum Propagation Delay, Enable to Analog Output (Figure 11) 2.0 3.0 4.5 6.0 245 115 49 39 315 145 69 58 345 155 83 67 ns Cin Maximum Input Capacitance, Channel−Select or Enable Inputs 10 10 10 pF CI/O Maximum Capacitance Analog I/O 35 35 35 pF (All Switches Off) Common O/I: HC4051A HC4052A HC4053A 130 80 50 130 80 50 130 80 50 Feedthrough 1.0 1.0 1.0 NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D) CPD Power Dissipation Capacitance (Figure 13)* HC4051A HC4052A HC4053A Typical @ 25 °C, VCC = 5.0 V, VEE = 0 V pF 45 80 45 * Used to determine the no−load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D). |
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