MC74HCT374A

http://onsemi.com

4

Symbol

Parameter

Guaranteed Limit

Unit

– 55 to 25

_C

v 85_C

v 125_C

Maximum Clock Frequency (50% Duty Cycle)

(Figures 1 and 4)

30

24

20

MHz

Maximum Propagation Delay, Clock to Q

(Figures 1 and 4)

31

39

47

ns

Maximum Propagation Delay, Output Enable to Q

(Figures 2 and 5)

30

38

45

ns

Maximum Propagation Delay, Output Enable to Q

(Figures 2 and 5)

30

38

45

ns

Maximum Output Transition Time, Any Output

(Figures 1 and 4)

12

15

18

ns

Maximum Input Capacitance

10

10

10

pF

Maximum Three−State Output Capacitance

(Output in High−Impedance State)

15

15

15

pF

For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON

Semiconductor High−Speed CMOS Data Book (DL129/D)

Typical @ 25

Power Dissipation Capacitance (Per Flip−Flop)*

65

pF

ON Semiconductor High−Speed CMOS Data Book (DL129/D).

Symbol

Parameter

Guaranteed Limit

Unit

– 55 to 25

_C

v 85_C

v 125_C

Minimum Setup Time, Data to Clock

(Figure 3)

12

15

18

ns

Minimum Hold Time, Clock to Data

(Figure 3)

5.0

5.0

5.0

ns

Minimum Pulse Width, Clock

(Figure 1)

12

15

18

ns

Maximum Input Rise and Fall Times

(Figure 1)

500

500

500

ns