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MC74HC4052ADG Datasheet(PDF) 3 Page - ON Semiconductor |
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MC74HC4052ADG Datasheet(HTML) 3 Page - ON Semiconductor |
3 / 18 page MC74HC4051A, MC74HC4052A, MC74HC4053A http://onsemi.com 3 LOGIC DIAGRAM MC74HC4053A Triple Single−Pole, Double−Position Plus Common Off X0 12 X1 13 A 11 B 10 C 9 ENABLE 6 X SWITCH Y SWITCH X 14 ANALOG INPUTS/OUTPUTS CHANNEL-SELECT INPUTS PIN 16 = VCC PIN 7 = VEE PIN 8 = GND COMMON OUTPUTS/INPUTS L L L L H H H H X L L H H L L H H X L H L H L H L H X FUNCTION TABLE − MC74HC4053A Control Inputs ON Channels Enable Select CB A L L L L L L L L H X = Don’t Care Pinout: MC74HC4053A (Top View) 15 16 14 13 12 11 10 2 1 34567 VCC 9 8 YX X1 X0 ABC Y1 Y0 Z1 Z Z0 Enable VEE GND Z0 Z0 Z0 Z0 Z1 Z1 Z1 Z1 Y0 Y0 Y1 Y1 Y0 Y0 Y1 Y1 X0 X1 X0 X1 X0 X1 X0 X1 NONE Y0 2 Y1 1 Y 15 Z0 5 Z1 3 Z 4 Z SWITCH NOTE: This device allows independent control of each switch. Channel−Select Input A controls the X−Switch, Input B controls the Y−Switch and Input C controls the Z−Switch MAXIMUM RATINGS Symbol Parameter Value Unit VCC Positive DC Supply Voltage (Referenced to GND) (Referenced to VEE) – 0.5 to + 7.0 – 0.5 to + 14.0 V VEE Negative DC Supply Voltage (Referenced to GND) – 7.0 to + 5.0 V VIS Analog Input Voltage VEE − 0.5 to VCC + 0.5 V Vin Digital Input Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V I DC Current, Into or Out of Any Pin ± 25 mA PD Power Dissipation in Still Air, Plastic DIP† EIAJ/SOIC Package† TSSOP Package† 750 500 450 mW Tstg Storage Temperature Range – 65 to + 150 _C TL Lead Temperature, 1 mm from Case for 10 Seconds Plastic DIP, SOIC or TSSOP Package 260 _C Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. †Derating — Plastic DIP: – 10 mW/ _C from 65_ to 125_C EIAJ/SOIC Package: – 7 mW/ _C from 65_ to 125_C TSSOP Package: − 6.1 mW/ _C from 65_ to 125_C For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D). This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance cir- cuit. For proper operation, Vin and Vout should be constrained to the range GND v (Vin or Vout) v VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. |
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