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MT9196AE1 Datasheet(PDF) 1 Page - Zarlink Semiconductor Inc

Part # MT9196AE1
Description  Integrated Digital Phone Circuit (IDPC)
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Manufacturer  ZARLINK [Zarlink Semiconductor Inc]
Direct Link  http://www.zarlink.com
Logo ZARLINK - Zarlink Semiconductor Inc

MT9196AE1 Datasheet(HTML) 1 Page - Zarlink Semiconductor Inc

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Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 1995-2005, Zarlink Semiconductor Inc. All Rights Reserved.
Features
Programmable m-Law/A-Law CODEC and
Filters
Programmable CCITT (G.711)/sign-magnitude
coding
Programmable transmit, receive and side-tone
gains
Digital DTMF and single tone generation
Fully differential interface to handset
transducers
Auxiliary analog interface
Interface to ST-BUS/SSI (compatible with GCI)
Serial microport control
Single 5 volt supply, low power operation
Anti-howl circuit for group listening
speakerphone applications
Applications
Digital telephone sets
Wireless telephones
Local area communications stations
Description
The MT9196 Integrated Digital Phone Circuit (IDPC) is
designed for use in digital phone products. The device
incorporates a built-in Filter/Codec, digital gain pads,
DTMF generator and tone ringer. Complete telephony
interfaces are provided for connecting to handset and
speakerphone transducers. Internal register access is
provided through a serial microport compatible with
various industry standard micro-controllers.
The device is fabricated in Zarlink's ISO2-CMOS
technology ensuring low power consumption and high
reliability.
January 2006
Ordering Information
MT9196AP
28 Pin PLCC
Tubes
MT9196AE
28 Pin PDIP
Tubes
MT9196AS
28 Pin SOIC
Tubes
MT9196ASR
28 Pin SOIC
Tape & Reel
MT9196APR
28 Pin PLCC
Tape & Reel
MT9196AE1
28 Pin PDIP*
Tubes
MT9196APR1
28 Pin PLCC*
Tape & Reel
MT9196AP1
28 Pin PLCC*
Tubes
MT9196AS1
28 Pin SOIC*
Tubes
MT9196ASR1
28 Pin SOIC*
Tape & Reel
*Pb Free Matte Tin
-40
°C to +85°C
ISO2-CMOS
MT9196
Integrated Digital Phone Circuit (IDPC)
Data Sheet
Figure 1 - Functional Block Diagram
VSSD
VDD
VSSA
VSS SPKR
VBias
VRef
Din
Dout
STB/F0i
CLOCKin
XSTL2
WD
PWRST
IC
CS
DATA1
DATA2
SCLK
AUXin
AUXout
MIC +
M -
M +
HSPKR +
HSPKR -
SPKR +
SPKR -
Digital Gain & Tone Generator
Filter/Codec Gain
21/ - 24dB
∆3.0dB
Tx & Rx
Encoder
Decoder
7dB
-7dB
Transducer
Interface
Flexible
Digital
Interface
Timing
ST-BUS
C & D
Channels
Serial Microport
IRQ


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